1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * 4 * Common functions for OMAP4/5 based boards 5 * 6 * (C) Copyright 2010 7 * Texas Instruments, <www.ti.com> 8 * 9 * Author : 10 * Aneesh V <aneesh@ti.com> 11 * Steve Sakoman <steve@sakoman.com> 12 */ 13 14 #include <common.h> 15 #include <cpu_func.h> 16 #include <asm/cache.h> 17 18 DECLARE_GLOBAL_DATA_PTR; 19 20 /* 21 * Without LPAE short descriptors are used 22 * Set C - Cache Bit3 23 * Set B - Buffer Bit2 24 * The last 2 bits set to 0b10 25 * Do Not set XN bit4 26 * So value is 0xe 27 * 28 * With LPAE cache configuration happens via MAIR0 register 29 * AttrIndx value is 0x3 for picking byte3 for MAIR0 which has 0xFF. 30 * 0xFF maps to Cache writeback with Read and Write Allocate set 31 * The bits[1:0] should have the value 0b01 for the first level 32 * descriptor. 33 * So the value is 0xd 34 */ 35 36 #ifdef CONFIG_ARMV7_LPAE 37 #define ARMV7_DCACHE_POLICY DCACHE_WRITEALLOC 38 #else 39 #define ARMV7_DCACHE_POLICY DCACHE_WRITEBACK & ~TTB_SECT_XN_MASK 40 #endif 41 42 #define ARMV7_DOMAIN_CLIENT 1 43 #define ARMV7_DOMAIN_MASK (0x3 << 0) 44 enable_caches(void)45void enable_caches(void) 46 { 47 48 /* Enable I cache if not enabled */ 49 if (!icache_status()) 50 icache_enable(); 51 52 dcache_enable(); 53 } 54 dram_bank_mmu_setup(int bank)55void dram_bank_mmu_setup(int bank) 56 { 57 bd_t *bd = gd->bd; 58 int i; 59 60 u32 start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT; 61 u32 size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT; 62 u32 end = start + size; 63 64 debug("%s: bank: %d\n", __func__, bank); 65 for (i = start; i < end; i++) 66 set_section_dcache(i, ARMV7_DCACHE_POLICY); 67 } 68 arm_init_domains(void)69void arm_init_domains(void) 70 { 71 u32 reg; 72 73 reg = get_dacr(); 74 /* 75 * Set DOMAIN to client access so that all permissions 76 * set in pagetables are validated by the mmu. 77 */ 78 reg &= ~ARMV7_DOMAIN_MASK; 79 reg |= ARMV7_DOMAIN_CLIENT; 80 set_dacr(reg); 81 } 82