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1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  *
4  * Common board functions for OMAP3 based boards.
5  *
6  * (C) Copyright 2004-2008
7  * Texas Instruments, <www.ti.com>
8  *
9  * Author :
10  *      Sunil Kumar <sunilsaini05@gmail.com>
11  *      Shashi Ranjan <shashiranjanmca05@gmail.com>
12  *
13  * Derived from Beagle Board and 3430 SDP code by
14  *      Richard Woodruff <r-woodruff2@ti.com>
15  *      Syed Mohammed Khasim <khasim@ti.com>
16  *
17  */
18 #include <common.h>
19 #include <dm.h>
20 #include <spl.h>
21 #include <asm/io.h>
22 #include <asm/arch/sys_proto.h>
23 #include <asm/arch/mem.h>
24 #include <asm/cache.h>
25 #include <asm/armv7.h>
26 #include <asm/gpio.h>
27 #include <asm/omap_common.h>
28 #include <linux/compiler.h>
29 
30 /* Declarations */
31 extern omap3_sysinfo sysinfo;
32 #ifndef CONFIG_SYS_L2CACHE_OFF
33 static void omap3_invalidate_l2_cache_secure(void);
34 #endif
35 
36 #ifdef CONFIG_DM_GPIO
37 #if !CONFIG_IS_ENABLED(OF_CONTROL)
38 /* Manually initialize GPIO banks when OF_CONTROL doesn't */
39 static const struct omap_gpio_platdata omap34xx_gpio[] = {
40 	{ 0, OMAP34XX_GPIO1_BASE },
41 	{ 1, OMAP34XX_GPIO2_BASE },
42 	{ 2, OMAP34XX_GPIO3_BASE },
43 	{ 3, OMAP34XX_GPIO4_BASE },
44 	{ 4, OMAP34XX_GPIO5_BASE },
45 	{ 5, OMAP34XX_GPIO6_BASE },
46 };
47 
48 U_BOOT_DEVICES(omap34xx_gpios) = {
49 	{ "gpio_omap", &omap34xx_gpio[0] },
50 	{ "gpio_omap", &omap34xx_gpio[1] },
51 	{ "gpio_omap", &omap34xx_gpio[2] },
52 	{ "gpio_omap", &omap34xx_gpio[3] },
53 	{ "gpio_omap", &omap34xx_gpio[4] },
54 	{ "gpio_omap", &omap34xx_gpio[5] },
55 };
56 #endif
57 #else
58 
59 static const struct gpio_bank gpio_bank_34xx[6] = {
60 	{ (void *)OMAP34XX_GPIO1_BASE },
61 	{ (void *)OMAP34XX_GPIO2_BASE },
62 	{ (void *)OMAP34XX_GPIO3_BASE },
63 	{ (void *)OMAP34XX_GPIO4_BASE },
64 	{ (void *)OMAP34XX_GPIO5_BASE },
65 	{ (void *)OMAP34XX_GPIO6_BASE },
66 };
67 
68 const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx;
69 
70 #endif
71 
72 /******************************************************************************
73  * Routine: secure_unlock
74  * Description: Setup security registers for access
75  *              (GP Device only)
76  *****************************************************************************/
secure_unlock_mem(void)77 void secure_unlock_mem(void)
78 {
79 	struct pm *pm_rt_ape_base = (struct pm *)PM_RT_APE_BASE_ADDR_ARM;
80 	struct pm *pm_gpmc_base = (struct pm *)PM_GPMC_BASE_ADDR_ARM;
81 	struct pm *pm_ocm_ram_base = (struct pm *)PM_OCM_RAM_BASE_ADDR_ARM;
82 	struct pm *pm_iva2_base = (struct pm *)PM_IVA2_BASE_ADDR_ARM;
83 	struct sms *sms_base = (struct sms *)OMAP34XX_SMS_BASE;
84 
85 	/* Protection Module Register Target APE (PM_RT) */
86 	writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
87 	writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0);
88 	writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0);
89 	writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1);
90 
91 	writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0);
92 	writel(UNLOCK_3, &pm_gpmc_base->read_permission_0);
93 	writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0);
94 
95 	writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0);
96 	writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0);
97 	writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0);
98 	writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2);
99 
100 	/* IVA Changes */
101 	writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0);
102 	writel(UNLOCK_3, &pm_iva2_base->read_permission_0);
103 	writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0);
104 
105 	/* SDRC region 0 public */
106 	writel(UNLOCK_1, &sms_base->rg_att0);
107 }
108 
109 /******************************************************************************
110  * Routine: secureworld_exit()
111  * Description: If chip is EMU and boot type is external
112  *		configure secure registers and exit secure world
113  *              general use.
114  *****************************************************************************/
secureworld_exit(void)115 void secureworld_exit(void)
116 {
117 	unsigned long i;
118 
119 	/* configure non-secure access control register */
120 	__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
121 	/* enabling co-processor CP10 and CP11 accesses in NS world */
122 	__asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
123 	/*
124 	 * allow allocation of locked TLBs and L2 lines in NS world
125 	 * allow use of PLE registers in NS world also
126 	 */
127 	__asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
128 	__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));
129 
130 	/* Enable ASA in ACR register */
131 	__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
132 	__asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
133 	__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
134 
135 	/* Exiting secure world */
136 	__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
137 	__asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
138 	__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
139 }
140 
141 /******************************************************************************
142  * Routine: try_unlock_sram()
143  * Description: If chip is GP/EMU(special) type, unlock the SRAM for
144  *              general use.
145  *****************************************************************************/
try_unlock_memory(void)146 void try_unlock_memory(void)
147 {
148 	int mode;
149 	int in_sdram = is_running_in_sdram();
150 
151 	/*
152 	 * if GP device unlock device SRAM for general use
153 	 * secure code breaks for Secure/Emulation device - HS/E/T
154 	 */
155 	mode = get_device_type();
156 	if (mode == GP_DEVICE)
157 		secure_unlock_mem();
158 
159 	/*
160 	 * If device is EMU and boot is XIP external booting
161 	 * Unlock firewalls and disable L2 and put chip
162 	 * out of secure world
163 	 *
164 	 * Assuming memories are unlocked by the demon who put us in SDRAM
165 	 */
166 	if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
167 	    && (!in_sdram)) {
168 		secure_unlock_mem();
169 		secureworld_exit();
170 	}
171 
172 	return;
173 }
174 
early_system_init(void)175 void early_system_init(void)
176 {
177 	hw_data_init();
178 }
179 
180 /******************************************************************************
181  * Routine: s_init
182  * Description: Does early system init of muxing and clocks.
183  *              - Called path is with SRAM stack.
184  *****************************************************************************/
s_init(void)185 void s_init(void)
186 {
187 	watchdog_init();
188 	early_system_init();
189 
190 	try_unlock_memory();
191 
192 #ifndef CONFIG_SYS_L2CACHE_OFF
193 	/* Invalidate L2-cache from secure mode */
194 	omap3_invalidate_l2_cache_secure();
195 #endif
196 
197 	set_muxconf_regs();
198 	sdelay(100);
199 
200 	prcm_init();
201 
202 	per_clocks_enable();
203 
204 #ifdef CONFIG_USB_EHCI_OMAP
205 	ehci_clocks_enable();
206 #endif
207 }
208 
209 #ifdef CONFIG_SPL_BUILD
board_init_f(ulong dummy)210 void board_init_f(ulong dummy)
211 {
212 	early_system_init();
213 	mem_init();
214 	/*
215 	* Save the boot parameters passed from romcode.
216 	* We cannot delay the saving further than this,
217 	* to prevent overwrites.
218 	*/
219 	save_omap_boot_params();
220 }
221 #endif
222 
223 /*
224  * Routine: misc_init_r
225  * Description: A basic misc_init_r that just displays the die ID
226  */
misc_init_r(void)227 int __weak misc_init_r(void)
228 {
229 	omap_die_id_display();
230 
231 	return 0;
232 }
233 
234 /******************************************************************************
235  * Routine: wait_for_command_complete
236  * Description: Wait for posting to finish on watchdog
237  *****************************************************************************/
wait_for_command_complete(struct watchdog * wd_base)238 static void wait_for_command_complete(struct watchdog *wd_base)
239 {
240 	int pending = 1;
241 	do {
242 		pending = readl(&wd_base->wwps);
243 	} while (pending);
244 }
245 
246 /******************************************************************************
247  * Routine: watchdog_init
248  * Description: Shut down watch dogs
249  *****************************************************************************/
watchdog_init(void)250 void watchdog_init(void)
251 {
252 	struct watchdog *wd2_base = (struct watchdog *)WD2_BASE;
253 	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
254 
255 	/*
256 	 * There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
257 	 * either taken care of by ROM (HS/EMU) or not accessible (GP).
258 	 * We need to take care of WD2-MPU or take a PRCM reset. WD3
259 	 * should not be running and does not generate a PRCM reset.
260 	 */
261 
262 	setbits_le32(&prcm_base->fclken_wkup, 0x20);
263 	setbits_le32(&prcm_base->iclken_wkup, 0x20);
264 	wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);
265 
266 	writel(WD_UNLOCK1, &wd2_base->wspr);
267 	wait_for_command_complete(wd2_base);
268 	writel(WD_UNLOCK2, &wd2_base->wspr);
269 }
270 
271 /******************************************************************************
272  * Dummy function to handle errors for EABI incompatibility
273  *****************************************************************************/
abort(void)274 void abort(void)
275 {
276 }
277 
278 #if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_SPL_BUILD)
279 /******************************************************************************
280  * OMAP3 specific command to switch between NAND HW and SW ecc
281  *****************************************************************************/
do_switch_ecc(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])282 static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
283 {
284 	int hw, strength = 1;
285 
286 	if (argc < 2 || argc > 3)
287 		goto usage;
288 
289 	if (strncmp(argv[1], "hw", 2) == 0) {
290 		hw = 1;
291 		if (argc == 3) {
292 			if (strncmp(argv[2], "bch8", 4) == 0)
293 				strength = 8;
294 			else if (strncmp(argv[2], "bch16", 5) == 0)
295 				strength = 16;
296 			else if (strncmp(argv[2], "hamming", 7) != 0)
297 				goto usage;
298 		}
299 	} else if (strncmp(argv[1], "sw", 2) == 0) {
300 		hw = 0;
301 		if (argc == 3) {
302 			if (strncmp(argv[2], "bch8", 4) == 0)
303 				strength = 8;
304 			else if (strncmp(argv[2], "hamming", 7) != 0)
305 				goto usage;
306 		}
307 	} else {
308 		goto usage;
309 	}
310 
311 	return -omap_nand_switch_ecc(hw, strength);
312 
313 usage:
314 	printf ("Usage: nandecc %s\n", cmdtp->usage);
315 	return 1;
316 }
317 
318 U_BOOT_CMD(
319 	nandecc, 3, 1,	do_switch_ecc,
320 	"switch OMAP3 NAND ECC calculation algorithm",
321 	"hw [hamming|bch8|bch16] - Switch between NAND hardware 1-bit hamming"
322 	" and 8-bit/16-bit BCH\n"
323 	"                           ecc calculation (second parameter may"
324 	" be omitted).\n"
325 	"nandecc sw               - Switch to NAND software ecc algorithm."
326 );
327 
328 #endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */
329 
330 #ifdef CONFIG_DISPLAY_BOARDINFO
331 /**
332  * Print board information
333  */
checkboard(void)334 int checkboard (void)
335 {
336 	char *mem_s ;
337 
338 	if (is_mem_sdr())
339 		mem_s = "mSDR";
340 	else
341 		mem_s = "LPDDR";
342 
343 	printf("%s + %s/%s\n", sysinfo.board_string, mem_s,
344 			sysinfo.nand_string);
345 
346 	return 0;
347 }
348 #endif	/* CONFIG_DISPLAY_BOARDINFO */
349 
omap3_emu_romcode_call(u32 service_id,u32 * parameters)350 static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
351 {
352 	u32 i, num_params = *parameters;
353 	u32 *sram_scratch_space = (u32 *)OMAP3_PUBLIC_SRAM_SCRATCH_AREA;
354 
355 	/*
356 	 * copy the parameters to an un-cached area to avoid coherency
357 	 * issues
358 	 */
359 	for (i = 0; i < num_params; i++) {
360 		__raw_writel(*parameters, sram_scratch_space);
361 		parameters++;
362 		sram_scratch_space++;
363 	}
364 
365 	/* Now make the PPA call */
366 	do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
367 }
368 
omap3_set_aux_cr_secure(u32 acr)369 void __weak omap3_set_aux_cr_secure(u32 acr)
370 {
371 	struct emu_hal_params emu_romcode_params;
372 
373 	emu_romcode_params.num_params = 1;
374 	emu_romcode_params.param1 = acr;
375 	omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
376 			       (u32 *)&emu_romcode_params);
377 }
378 
v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl,u32 cpu_midr,u32 cpu_rev_comb,u32 cpu_variant,u32 cpu_rev)379 void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
380 				 u32 cpu_rev_comb, u32 cpu_variant,
381 				 u32 cpu_rev)
382 {
383 	if (get_device_type() == GP_DEVICE)
384 		omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_L2ACR, l2auxctrl);
385 
386 	/* L2 Cache Auxiliary Control Register is not banked */
387 }
388 
v7_arch_cp15_set_acr(u32 acr,u32 cpu_midr,u32 cpu_rev_comb,u32 cpu_variant,u32 cpu_rev)389 void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
390 			  u32 cpu_variant, u32 cpu_rev)
391 {
392 	/* Write ACR - affects secure banked bits */
393 	if (get_device_type() == GP_DEVICE)
394 		omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_ACR, acr);
395 	else
396 		omap3_set_aux_cr_secure(acr);
397 
398 	/* Write ACR - affects non-secure banked bits - some erratas need it */
399 	asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
400 }
401 
402 
403 #ifndef CONFIG_SYS_L2CACHE_OFF
omap3_update_aux_cr(u32 set_bits,u32 clear_bits)404 static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
405 {
406 	u32 acr;
407 
408 	/* Read ACR */
409 	asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
410 	acr &= ~clear_bits;
411 	acr |= set_bits;
412 	v7_arch_cp15_set_acr(acr, 0, 0, 0, 0);
413 
414 }
415 
416 /* Invalidate the entire L2 cache from secure mode */
omap3_invalidate_l2_cache_secure(void)417 static void omap3_invalidate_l2_cache_secure(void)
418 {
419 	if (get_device_type() == GP_DEVICE) {
420 		omap_smc1(OMAP3_GP_ROMCODE_API_L2_INVAL, 0);
421 	} else {
422 		struct emu_hal_params emu_romcode_params;
423 		emu_romcode_params.num_params = 1;
424 		emu_romcode_params.param1 = 0;
425 		omap3_emu_romcode_call(OMAP3_EMU_HAL_API_L2_INVAL,
426 				       (u32 *)&emu_romcode_params);
427 	}
428 }
429 
v7_outer_cache_enable(void)430 void v7_outer_cache_enable(void)
431 {
432 
433 	/*
434 	 * Set L2EN
435 	 * On some revisions L2EN bit is banked on some revisions it's not
436 	 * No harm in setting both banked bits(in fact this is required
437 	 * by an erratum)
438 	 */
439 	omap3_update_aux_cr(0x2, 0);
440 }
441 
omap3_outer_cache_disable(void)442 void omap3_outer_cache_disable(void)
443 {
444 	/*
445 	 * Clear L2EN
446 	 * On some revisions L2EN bit is banked on some revisions it's not
447 	 * No harm in clearing both banked bits(in fact this is required
448 	 * by an erratum)
449 	 */
450 	omap3_update_aux_cr(0, 0x2);
451 }
452 #endif /* !CONFIG_SYS_L2CACHE_OFF */
453