1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Renesas RCar Gen3 memory map tables
4 *
5 * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
6 */
7
8 #include <common.h>
9 #include <cpu_func.h>
10 #include <asm/armv8/mmu.h>
11
12 #define GEN3_NR_REGIONS 16
13
14 static struct mm_region gen3_mem_map[GEN3_NR_REGIONS] = {
15 {
16 .virt = 0x0UL,
17 .phys = 0x0UL,
18 .size = 0x40000000UL,
19 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
20 PTE_BLOCK_NON_SHARE |
21 PTE_BLOCK_PXN | PTE_BLOCK_UXN
22 }, {
23 .virt = 0x40000000UL,
24 .phys = 0x40000000UL,
25 .size = 0x03F00000UL,
26 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
27 PTE_BLOCK_INNER_SHARE
28 }, {
29 .virt = 0x47E00000UL,
30 .phys = 0x47E00000UL,
31 .size = 0x78200000UL,
32 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
33 PTE_BLOCK_INNER_SHARE
34 }, {
35 .virt = 0xc0000000UL,
36 .phys = 0xc0000000UL,
37 .size = 0x40000000UL,
38 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
39 PTE_BLOCK_NON_SHARE |
40 PTE_BLOCK_PXN | PTE_BLOCK_UXN
41 }, {
42 .virt = 0x100000000UL,
43 .phys = 0x100000000UL,
44 .size = 0xf00000000UL,
45 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
46 PTE_BLOCK_INNER_SHARE
47 }, {
48 /* List terminator */
49 0,
50 }
51 };
52
53 struct mm_region *mem_map = gen3_mem_map;
54
55 DECLARE_GLOBAL_DATA_PTR;
56
enable_caches(void)57 void enable_caches(void)
58 {
59 u64 start, size;
60 int bank, i = 0;
61
62 /* Create map for RPC access */
63 gen3_mem_map[i].virt = 0x0ULL;
64 gen3_mem_map[i].phys = 0x0ULL;
65 gen3_mem_map[i].size = 0x40000000ULL;
66 gen3_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
67 PTE_BLOCK_NON_SHARE |
68 PTE_BLOCK_PXN | PTE_BLOCK_UXN;
69 i++;
70
71 /* Generate entires for DRAM in 32bit address space */
72 for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
73 start = gd->bd->bi_dram[bank].start;
74 size = gd->bd->bi_dram[bank].size;
75
76 /* Skip empty DRAM banks */
77 if (!size)
78 continue;
79
80 /* Skip DRAM above 4 GiB */
81 if (start >> 32ULL)
82 continue;
83
84 /* Mark memory reserved by ATF as cacheable too. */
85 if (start == 0x48000000) {
86 /* Unmark protection area (0x43F00000 to 0x47DFFFFF) */
87 gen3_mem_map[i].virt = 0x40000000ULL;
88 gen3_mem_map[i].phys = 0x40000000ULL;
89 gen3_mem_map[i].size = 0x03F00000ULL;
90 gen3_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
91 PTE_BLOCK_INNER_SHARE;
92 i++;
93
94 start = 0x47E00000ULL;
95 size += 0x00200000ULL;
96 }
97
98 gen3_mem_map[i].virt = start;
99 gen3_mem_map[i].phys = start;
100 gen3_mem_map[i].size = size;
101 gen3_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
102 PTE_BLOCK_INNER_SHARE;
103 i++;
104 }
105
106 /* Create map for register access */
107 gen3_mem_map[i].virt = 0xc0000000ULL;
108 gen3_mem_map[i].phys = 0xc0000000ULL;
109 gen3_mem_map[i].size = 0x40000000ULL;
110 gen3_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
111 PTE_BLOCK_NON_SHARE |
112 PTE_BLOCK_PXN | PTE_BLOCK_UXN;
113 i++;
114
115 /* Generate entires for DRAM in 64bit address space */
116 for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
117 start = gd->bd->bi_dram[bank].start;
118 size = gd->bd->bi_dram[bank].size;
119
120 /* Skip empty DRAM banks */
121 if (!size)
122 continue;
123
124 /* Skip DRAM below 4 GiB */
125 if (!(start >> 32ULL))
126 continue;
127
128 gen3_mem_map[i].virt = start;
129 gen3_mem_map[i].phys = start;
130 gen3_mem_map[i].size = size;
131 gen3_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
132 PTE_BLOCK_INNER_SHARE;
133 i++;
134 }
135
136 /* Zero out the remaining regions. */
137 for (; i < GEN3_NR_REGIONS; i++) {
138 gen3_mem_map[i].virt = 0;
139 gen3_mem_map[i].phys = 0;
140 gen3_mem_map[i].size = 0;
141 gen3_mem_map[i].attrs = 0;
142 }
143
144 if (!icache_status())
145 icache_enable();
146
147 dcache_enable();
148 }
149