1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2016 Rockchip Electronics Co., Ltd
4 */
5
6 #include <common.h>
7 #include <spl.h>
8 #include <spl_gpio.h>
9 #include <syscon.h>
10 #include <asm/armv8/mmu.h>
11 #include <asm/io.h>
12 #include <asm/arch-rockchip/bootrom.h>
13 #include <asm/arch-rockchip/clock.h>
14 #include <asm/arch-rockchip/gpio.h>
15 #include <asm/arch-rockchip/grf_rk3399.h>
16 #include <asm/arch-rockchip/hardware.h>
17 #include <power/regulator.h>
18
19 DECLARE_GLOBAL_DATA_PTR;
20
21 #define GRF_EMMCCORE_CON11 0xff77f02c
22 #define GRF_BASE 0xff770000
23
24 const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
25 [BROM_BOOTSOURCE_EMMC] = "/sdhci@fe330000",
26 [BROM_BOOTSOURCE_SPINOR] = "/spi@ff1d0000",
27 [BROM_BOOTSOURCE_SD] = "/dwmmc@fe320000",
28 };
29
30 static struct mm_region rk3399_mem_map[] = {
31 {
32 .virt = 0x0UL,
33 .phys = 0x0UL,
34 .size = 0xf8000000UL,
35 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
36 PTE_BLOCK_INNER_SHARE
37 }, {
38 .virt = 0xf8000000UL,
39 .phys = 0xf8000000UL,
40 .size = 0x08000000UL,
41 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
42 PTE_BLOCK_NON_SHARE |
43 PTE_BLOCK_PXN | PTE_BLOCK_UXN
44 }, {
45 /* List terminator */
46 0,
47 }
48 };
49
50 struct mm_region *mem_map = rk3399_mem_map;
51
52 #ifdef CONFIG_SPL_BUILD
53
54 #define TIMER_END_COUNT_L 0x00
55 #define TIMER_END_COUNT_H 0x04
56 #define TIMER_INIT_COUNT_L 0x10
57 #define TIMER_INIT_COUNT_H 0x14
58 #define TIMER_CONTROL_REG 0x1c
59
60 #define TIMER_EN 0x1
61 #define TIMER_FMODE BIT(0)
62 #define TIMER_RMODE BIT(1)
63
rockchip_stimer_init(void)64 void rockchip_stimer_init(void)
65 {
66 /* If Timer already enabled, don't re-init it */
67 u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
68
69 if (reg & TIMER_EN)
70 return;
71
72 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_END_COUNT_L);
73 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_END_COUNT_H);
74 writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_INIT_COUNT_L);
75 writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_INIT_COUNT_H);
76 writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE + \
77 TIMER_CONTROL_REG);
78 }
79 #endif
80
arch_cpu_init(void)81 int arch_cpu_init(void)
82 {
83
84 #ifdef CONFIG_SPL_BUILD
85 struct rk3399_pmusgrf_regs *sgrf;
86 struct rk3399_grf_regs *grf;
87
88 /*
89 * Disable DDR and SRAM security regions.
90 *
91 * As we are entered from the BootROM, the region from
92 * 0x0 through 0xfffff (i.e. the first MB of memory) will
93 * be protected. This will cause issues with the DW_MMC
94 * driver, which tries to DMA from/to the stack (likely)
95 * located in this range.
96 */
97 sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
98 rk_clrsetreg(&sgrf->ddr_rgn_con[16], 0x1ff, 0);
99 rk_clrreg(&sgrf->slv_secure_con4, 0x2000);
100
101 /* eMMC clock generator: disable the clock multipilier */
102 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
103 rk_clrreg(&grf->emmccore_con[11], 0x0ff);
104 #endif
105
106 return 0;
107 }
108
109 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
board_debug_uart_init(void)110 void board_debug_uart_init(void)
111 {
112 #define GRF_BASE 0xff770000
113 #define GPIO0_BASE 0xff720000
114 #define PMUGRF_BASE 0xff320000
115 struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
116 #ifdef CONFIG_TARGET_CHROMEBOOK_BOB
117 struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE;
118 struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE;
119 #endif
120
121 #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
122 /* Enable early UART0 on the RK3399 */
123 rk_clrsetreg(&grf->gpio2c_iomux,
124 GRF_GPIO2C0_SEL_MASK,
125 GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT);
126 rk_clrsetreg(&grf->gpio2c_iomux,
127 GRF_GPIO2C1_SEL_MASK,
128 GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT);
129 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff1B0000)
130 /* Enable early UART3 on the RK3399 */
131 rk_clrsetreg(&grf->gpio3b_iomux,
132 GRF_GPIO3B6_SEL_MASK,
133 GRF_UART3_SIN << GRF_GPIO3B6_SEL_SHIFT);
134 rk_clrsetreg(&grf->gpio3b_iomux,
135 GRF_GPIO3B7_SEL_MASK,
136 GRF_UART3_SOUT << GRF_GPIO3B7_SEL_SHIFT);
137 #else
138 # ifdef CONFIG_TARGET_CHROMEBOOK_BOB
139 rk_setreg(&grf->io_vsel, 1 << 0);
140
141 /*
142 * Let's enable these power rails here, we are already running the SPI
143 * Flash based code.
144 */
145 spl_gpio_output(gpio, GPIO(BANK_B, 2), 1); /* PP1500_EN */
146 spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 2), GPIO_PULL_NORMAL);
147
148 spl_gpio_output(gpio, GPIO(BANK_B, 4), 1); /* PP3000_EN */
149 spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 4), GPIO_PULL_NORMAL);
150 #endif /* CONFIG_TARGET_CHROMEBOOK_BOB */
151
152 /* Enable early UART2 channel C on the RK3399 */
153 rk_clrsetreg(&grf->gpio4c_iomux,
154 GRF_GPIO4C3_SEL_MASK,
155 GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
156 rk_clrsetreg(&grf->gpio4c_iomux,
157 GRF_GPIO4C4_SEL_MASK,
158 GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
159 /* Set channel C as UART2 input */
160 rk_clrsetreg(&grf->soc_con7,
161 GRF_UART_DBG_SEL_MASK,
162 GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT);
163 #endif
164 }
165 #endif
166
167 #if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
spl_decode_boot_device(u32 boot_device)168 const char *spl_decode_boot_device(u32 boot_device)
169 {
170 int i;
171 static const struct {
172 u32 boot_device;
173 const char *ofpath;
174 } spl_boot_devices_tbl[] = {
175 { BOOT_DEVICE_MMC1, "/dwmmc@fe320000" },
176 { BOOT_DEVICE_MMC2, "/sdhci@fe330000" },
177 { BOOT_DEVICE_SPI, "/spi@ff1d0000" },
178 };
179
180 for (i = 0; i < ARRAY_SIZE(spl_boot_devices_tbl); ++i)
181 if (spl_boot_devices_tbl[i].boot_device == boot_device)
182 return spl_boot_devices_tbl[i].ofpath;
183
184 return NULL;
185 }
186
spl_perform_fixups(struct spl_image_info * spl_image)187 void spl_perform_fixups(struct spl_image_info *spl_image)
188 {
189 void *blob = spl_image->fdt_addr;
190 const char *boot_ofpath;
191 int chosen;
192
193 /*
194 * Inject the ofpath of the device the full U-Boot (or Linux in
195 * Falcon-mode) was booted from into the FDT, if a FDT has been
196 * loaded at the same time.
197 */
198 if (!blob)
199 return;
200
201 boot_ofpath = spl_decode_boot_device(spl_image->boot_device);
202 if (!boot_ofpath) {
203 pr_err("%s: could not map boot_device to ofpath\n", __func__);
204 return;
205 }
206
207 chosen = fdt_find_or_add_subnode(blob, 0, "chosen");
208 if (chosen < 0) {
209 pr_err("%s: could not find/create '/chosen'\n", __func__);
210 return;
211 }
212 fdt_setprop_string(blob, chosen,
213 "u-boot,spl-boot-device", boot_ofpath);
214 }
215
216 #if defined(SPL_GPIO_SUPPORT)
rk3399_force_power_on_reset(void)217 static void rk3399_force_power_on_reset(void)
218 {
219 ofnode node;
220 struct gpio_desc sysreset_gpio;
221
222 debug("%s: trying to force a power-on reset\n", __func__);
223
224 node = ofnode_path("/config");
225 if (!ofnode_valid(node)) {
226 debug("%s: no /config node?\n", __func__);
227 return;
228 }
229
230 if (gpio_request_by_name_nodev(node, "sysreset-gpio", 0,
231 &sysreset_gpio, GPIOD_IS_OUT)) {
232 debug("%s: could not find a /config/sysreset-gpio\n", __func__);
233 return;
234 }
235
236 dm_gpio_set_value(&sysreset_gpio, 1);
237 }
238 #endif
239
spl_board_init(void)240 void spl_board_init(void)
241 {
242 #if defined(SPL_GPIO_SUPPORT)
243 struct rk3399_cru *cru = rockchip_get_cru();
244
245 /*
246 * The RK3399 resets only 'almost all logic' (see also in the TRM
247 * "3.9.4 Global software reset"), when issuing a software reset.
248 * This may cause issues during boot-up for some configurations of
249 * the application software stack.
250 *
251 * To work around this, we test whether the last reset reason was
252 * a power-on reset and (if not) issue an overtemp-reset to reset
253 * the entire module.
254 *
255 * While this was previously fixed by modifying the various places
256 * that could generate a software reset (e.g. U-Boot's sysreset
257 * driver, the ATF or Linux), we now have it here to ensure that
258 * we no longer have to track this through the various components.
259 */
260 if (cru->glb_rst_st != 0)
261 rk3399_force_power_on_reset();
262 #endif
263
264 #if defined(SPL_DM_REGULATOR)
265 /*
266 * Turning the eMMC and SPI back on (if disabled via the Qseven
267 * BIOS_ENABLE) signal is done through a always-on regulator).
268 */
269 if (regulators_enable_boot_on(false))
270 debug("%s: Cannot enable boot on regulator\n", __func__);
271 #endif
272 }
273 #endif
274