1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2012-2019 Altera Corporation <www.altera.com>
4 */
5
6 #include <common.h>
7 #include <cpu_func.h>
8 #include <asm/io.h>
9 #include <asm/pl310.h>
10 #include <asm/u-boot.h>
11 #include <asm/utils.h>
12 #include <image.h>
13 #include <asm/arch/reset_manager.h>
14 #include <spl.h>
15 #include <asm/arch/system_manager.h>
16 #include <asm/arch/freeze_controller.h>
17 #include <asm/arch/clock_manager.h>
18 #include <asm/arch/scan_manager.h>
19 #include <asm/arch/sdram.h>
20 #include <asm/arch/scu.h>
21 #include <asm/arch/misc.h>
22 #include <asm/arch/nic301.h>
23 #include <asm/sections.h>
24 #include <fdtdec.h>
25 #include <watchdog.h>
26 #include <asm/arch/pinmux.h>
27 #include <asm/arch/fpga_manager.h>
28 #include <mmc.h>
29 #include <memalign.h>
30
31 #define FPGA_BUFSIZ 16 * 1024
32
33 DECLARE_GLOBAL_DATA_PTR;
34
35 static const struct socfpga_system_manager *sysmgr_regs =
36 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
37
spl_boot_device(void)38 u32 spl_boot_device(void)
39 {
40 const u32 bsel = readl(&sysmgr_regs->bootinfo);
41
42 switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
43 case 0x1: /* FPGA (HPS2FPGA Bridge) */
44 return BOOT_DEVICE_RAM;
45 case 0x2: /* NAND Flash (1.8V) */
46 case 0x3: /* NAND Flash (3.0V) */
47 socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
48 return BOOT_DEVICE_NAND;
49 case 0x4: /* SD/MMC External Transceiver (1.8V) */
50 case 0x5: /* SD/MMC Internal Transceiver (3.0V) */
51 socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);
52 socfpga_per_reset(SOCFPGA_RESET(DMA), 0);
53 return BOOT_DEVICE_MMC1;
54 case 0x6: /* QSPI Flash (1.8V) */
55 case 0x7: /* QSPI Flash (3.0V) */
56 socfpga_per_reset(SOCFPGA_RESET(QSPI), 0);
57 return BOOT_DEVICE_SPI;
58 default:
59 printf("Invalid boot device (bsel=%08x)!\n", bsel);
60 hang();
61 }
62 }
63
64 #ifdef CONFIG_SPL_MMC_SUPPORT
spl_boot_mode(const u32 boot_device)65 u32 spl_boot_mode(const u32 boot_device)
66 {
67 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
68 return MMCSD_MODE_FS;
69 #else
70 return MMCSD_MODE_RAW;
71 #endif
72 }
73 #endif
74
spl_board_init(void)75 void spl_board_init(void)
76 {
77 ALLOC_CACHE_ALIGN_BUFFER(char, buf, FPGA_BUFSIZ);
78
79 /* enable console uart printing */
80 preloader_console_init();
81 WATCHDOG_RESET();
82
83 arch_early_init_r();
84
85 /* If the full FPGA is already loaded, ie.from EPCQ, config fpga pins */
86 if (is_fpgamgr_user_mode()) {
87 int ret = config_pins(gd->fdt_blob, "shared");
88
89 if (ret)
90 return;
91
92 ret = config_pins(gd->fdt_blob, "fpga");
93 if (ret)
94 return;
95 } else if (!is_fpgamgr_early_user_mode()) {
96 /* Program IOSSM(early IO release) or full FPGA */
97 fpgamgr_program(buf, FPGA_BUFSIZ, 0);
98 }
99
100 /* If the IOSSM/full FPGA is already loaded, start DDR */
101 if (is_fpgamgr_early_user_mode() || is_fpgamgr_user_mode())
102 ddr_calibration_sequence();
103
104 if (!is_fpgamgr_user_mode())
105 fpgamgr_program(buf, FPGA_BUFSIZ, 0);
106 }
107
board_init_f(ulong dummy)108 void board_init_f(ulong dummy)
109 {
110 dcache_disable();
111
112 socfpga_init_security_policies();
113 socfpga_sdram_remap_zero();
114 socfpga_pl310_clear();
115
116 /* Assert reset to all except L4WD0 and L4TIMER0 */
117 socfpga_per_reset_all();
118 socfpga_watchdog_disable();
119
120 spl_early_init();
121
122 /* Configure the clock based on handoff */
123 cm_basic_init(gd->fdt_blob);
124
125 #ifdef CONFIG_HW_WATCHDOG
126 /* release osc1 watchdog timer 0 from reset */
127 socfpga_reset_deassert_osc1wd0();
128
129 /* reconfigure and enable the watchdog */
130 hw_watchdog_init();
131 WATCHDOG_RESET();
132 #endif /* CONFIG_HW_WATCHDOG */
133
134 config_dedicated_pins(gd->fdt_blob);
135 WATCHDOG_RESET();
136 }
137