1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2015 - 2016 Xilinx, Inc.
4 *
5 * Michal Simek <michal.simek@xilinx.com>
6 */
7
8 #include <common.h>
9 #include <debug_uart.h>
10 #include <init.h>
11 #include <spl.h>
12
13 #include <asm/io.h>
14 #include <asm/spl.h>
15 #include <asm/arch/hardware.h>
16 #include <asm/arch/sys_proto.h>
17
board_init_f(ulong dummy)18 void board_init_f(ulong dummy)
19 {
20 board_early_init_f();
21 board_early_init_r();
22
23 #ifdef CONFIG_DEBUG_UART
24 /* Uart debug for sure */
25 debug_uart_init();
26 puts("Debug uart enabled\n"); /* or printch() */
27 #endif
28 /* Delay is required for clocks to be propagated */
29 udelay(1000000);
30
31 debug("Clearing BSS 0x%p - 0x%p\n", __bss_start, __bss_end);
32 /* Clear the BSS */
33 memset(__bss_start, 0, __bss_end - __bss_start);
34
35 /* No need to call timer init - it is empty for ZynqMP */
36 board_init_r(NULL, 0);
37 }
38
ps_mode_reset(ulong mode)39 static void ps_mode_reset(ulong mode)
40 {
41 writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT,
42 &crlapb_base->boot_pin_ctrl);
43 udelay(5);
44 writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT |
45 mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT,
46 &crlapb_base->boot_pin_ctrl);
47 }
48
49 /*
50 * Set default PS_MODE1 which is used for USB ULPI phy reset
51 * Also other resets can be connected to this certain pin
52 */
53 #ifndef MODE_RESET
54 # define MODE_RESET PS_MODE1
55 #endif
56
57 #ifdef CONFIG_SPL_BOARD_INIT
spl_board_init(void)58 void spl_board_init(void)
59 {
60 preloader_console_init();
61 ps_mode_reset(MODE_RESET);
62 board_init();
63 }
64 #endif
65
spl_boot_device(void)66 u32 spl_boot_device(void)
67 {
68 u32 reg = 0;
69 u8 bootmode;
70
71 #if defined(CONFIG_SPL_ZYNQMP_ALT_BOOTMODE_ENABLED)
72 /* Change default boot mode at run-time */
73 writel(CONFIG_SPL_ZYNQMP_ALT_BOOTMODE << BOOT_MODE_ALT_SHIFT,
74 &crlapb_base->boot_mode);
75 #endif
76
77 reg = readl(&crlapb_base->boot_mode);
78 if (reg >> BOOT_MODE_ALT_SHIFT)
79 reg >>= BOOT_MODE_ALT_SHIFT;
80
81 bootmode = reg & BOOT_MODES_MASK;
82
83 switch (bootmode) {
84 case JTAG_MODE:
85 return BOOT_DEVICE_RAM;
86 #ifdef CONFIG_SPL_MMC_SUPPORT
87 case SD_MODE1:
88 case SD1_LSHFT_MODE: /* not working on silicon v1 */
89 /* if both controllers enabled, then these two are the second controller */
90 #ifdef CONFIG_SPL_ZYNQMP_TWO_SDHCI
91 return BOOT_DEVICE_MMC2;
92 /* else, fall through, the one SDHCI controller that is enabled is number 1 */
93 #endif
94 case SD_MODE:
95 case EMMC_MODE:
96 return BOOT_DEVICE_MMC1;
97 #endif
98 #ifdef CONFIG_SPL_DFU
99 case USB_MODE:
100 return BOOT_DEVICE_DFU;
101 #endif
102 #ifdef CONFIG_SPL_SATA_SUPPORT
103 case SW_SATA_MODE:
104 return BOOT_DEVICE_SATA;
105 #endif
106 #ifdef CONFIG_SPL_SPI_SUPPORT
107 case QSPI_MODE_24BIT:
108 case QSPI_MODE_32BIT:
109 return BOOT_DEVICE_SPI;
110 #endif
111 default:
112 printf("Invalid Boot Mode:0x%x\n", bootmode);
113 break;
114 }
115
116 return 0;
117 }
118
119 #ifdef CONFIG_SPL_OS_BOOT
spl_start_uboot(void)120 int spl_start_uboot(void)
121 {
122 handoff_setup();
123
124 return 0;
125 }
126 #endif
127
128 #ifdef CONFIG_SPL_LOAD_FIT
board_fit_config_name_match(const char * name)129 int board_fit_config_name_match(const char *name)
130 {
131 /* Just empty function now - can't decide what to choose */
132 debug("%s: %s\n", __func__, name);
133
134 return 0;
135 }
136 #endif
137