1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 *
4 * (C) Copyright 2000-2003
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 *
7 * (C) Copyright 2004-2007, 2012 Freescale Semiconductor, Inc.
8 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
9 */
10
11 #include <common.h>
12 #include <cpu_func.h>
13 #include <watchdog.h>
14 #include <asm/immap.h>
15 #include <asm/processor.h>
16 #include <asm/rtc.h>
17 #include <asm/io.h>
18 #include <linux/compiler.h>
19
20 #if defined(CONFIG_CMD_NET)
21 #include <config.h>
22 #include <net.h>
23 #include <asm/fec.h>
24 #endif
25
init_fbcs(void)26 void init_fbcs(void)
27 {
28 fbcs_t *fbcs __maybe_unused = (fbcs_t *) MMAP_FBCS;
29
30 #if !defined(CONFIG_SERIAL_BOOT)
31 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
32 out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
33 out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
34 out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
35 #endif
36 #endif
37
38 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
39 /* Latch chipselect */
40 out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
41 out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
42 out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
43 #endif
44
45 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
46 out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
47 out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
48 out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
49 #endif
50
51 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
52 out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
53 out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
54 out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
55 #endif
56
57 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
58 out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
59 out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
60 out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
61 #endif
62
63 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
64 out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
65 out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
66 out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
67 #endif
68 }
69
70 #ifdef CONFIG_CF_DSPI
cfspi_port_conf(void)71 void cfspi_port_conf(void)
72 {
73 gpio_t *gpio = (gpio_t *)MMAP_GPIO;
74
75 #ifdef CONFIG_MCF5445x
76 out_8(&gpio->par_dspi,
77 GPIO_PAR_DSPI_SIN_SIN |
78 GPIO_PAR_DSPI_SOUT_SOUT |
79 GPIO_PAR_DSPI_SCK_SCK);
80 #endif
81
82 #ifdef CONFIG_MCF5441x
83 pm_t *pm = (pm_t *)MMAP_PM;
84
85 out_8(&gpio->par_dspi0,
86 GPIO_PAR_DSPI0_SIN_DSPI0SIN | GPIO_PAR_DSPI0_SOUT_DSPI0SOUT |
87 GPIO_PAR_DSPI0_SCK_DSPI0SCK);
88 out_8(&gpio->srcr_dspiow, 3);
89
90 /* DSPI0 */
91 out_8(&pm->pmcr0, 23);
92 #endif
93 }
94 #endif
95
96 /*
97 * Breath some life into the CPU...
98 *
99 * Set up the memory map,
100 * initialize a bunch of registers,
101 * initialize the UPM's
102 */
cpu_init_f(void)103 void cpu_init_f(void)
104 {
105 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
106
107 #ifdef CONFIG_MCF5441x
108 scm_t *scm = (scm_t *) MMAP_SCM;
109 pm_t *pm = (pm_t *) MMAP_PM;
110
111 /* Disable Switch */
112 *(unsigned long *)(MMAP_L2_SW0 + 0x00000024) = 0;
113
114 /* Disable core watchdog */
115 out_be16(&scm->cwcr, 0);
116 out_8(&gpio->par_fbctl,
117 GPIO_PAR_FBCTL_ALE_FB_ALE | GPIO_PAR_FBCTL_OE_FB_OE |
118 GPIO_PAR_FBCTL_FBCLK | GPIO_PAR_FBCTL_RW |
119 GPIO_PAR_FBCTL_TA_TA);
120 out_8(&gpio->par_be,
121 GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 |
122 GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0);
123
124 /* eDMA */
125 out_8(&pm->pmcr0, 17);
126
127 /* INTR0 - INTR2 */
128 out_8(&pm->pmcr0, 18);
129 out_8(&pm->pmcr0, 19);
130 out_8(&pm->pmcr0, 20);
131
132 /* I2C */
133 out_8(&pm->pmcr0, 22);
134 out_8(&pm->pmcr1, 4);
135 out_8(&pm->pmcr1, 7);
136
137 /* DTMR0 - DTMR3*/
138 out_8(&pm->pmcr0, 28);
139 out_8(&pm->pmcr0, 29);
140 out_8(&pm->pmcr0, 30);
141 out_8(&pm->pmcr0, 31);
142
143 /* PIT0 - PIT3 */
144 out_8(&pm->pmcr0, 32);
145 out_8(&pm->pmcr0, 33);
146 out_8(&pm->pmcr0, 34);
147 out_8(&pm->pmcr0, 35);
148
149 /* Edge Port */
150 out_8(&pm->pmcr0, 36);
151 out_8(&pm->pmcr0, 37);
152
153 /* USB OTG */
154 out_8(&pm->pmcr0, 44);
155 /* USB Host */
156 out_8(&pm->pmcr0, 45);
157
158 /* ESDHC */
159 out_8(&pm->pmcr0, 51);
160
161 /* ENET0 - ENET1 */
162 out_8(&pm->pmcr0, 53);
163 out_8(&pm->pmcr0, 54);
164
165 /* NAND */
166 out_8(&pm->pmcr0, 63);
167
168 #ifdef CONFIG_SYS_I2C_0
169 out_8(&gpio->par_cani2c, 0xF0);
170 /* I2C0 pull up */
171 out_be16(&gpio->pcr_b, 0x003C);
172 /* I2C0 max speed */
173 out_8(&gpio->srcr_cani2c, 0x03);
174 #endif
175 #ifdef CONFIG_SYS_I2C_2
176 /* I2C2 */
177 out_8(&gpio->par_ssi0h, 0xA0);
178 /* I2C2, UART7 */
179 out_8(&gpio->par_ssi0h, 0xA8);
180 /* UART7 */
181 out_8(&gpio->par_ssi0l, 0x2);
182 /* UART8, UART9 */
183 out_8(&gpio->par_cani2c, 0xAA);
184 /* UART4, UART0 */
185 out_8(&gpio->par_uart0, 0xAF);
186 /* UART5, UART1 */
187 out_8(&gpio->par_uart1, 0xAF);
188 /* UART6, UART2 */
189 out_8(&gpio->par_uart2, 0xAF);
190 /* I2C2 pull up */
191 out_be16(&gpio->pcr_h, 0xF000);
192 #endif
193 #ifdef CONFIG_SYS_I2C_5
194 /* I2C5 */
195 out_8(&gpio->par_uart1, 0x0A);
196 /* I2C5 pull up */
197 out_be16(&gpio->pcr_e, 0x0003);
198 out_be16(&gpio->pcr_f, 0xC000);
199 #endif
200
201 /* Lowest slew rate for UART0,1,2 */
202 out_8(&gpio->srcr_uart, 0x00);
203
204 #ifdef CONFIG_FSL_ESDHC_IMX
205 /* eSDHC pin as faster speed */
206 out_8(&gpio->srcr_sdhc, 0x03);
207
208 /* All esdhc pins as SD */
209 out_8(&gpio->par_sdhch, 0xff);
210 out_8(&gpio->par_sdhcl, 0xff);
211 #endif
212 #endif /* CONFIG_MCF5441x */
213
214 #ifdef CONFIG_MCF5445x
215 scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
216
217 out_be32(&scm1->mpr, 0x77777777);
218 out_be32(&scm1->pacra, 0);
219 out_be32(&scm1->pacrb, 0);
220 out_be32(&scm1->pacrc, 0);
221 out_be32(&scm1->pacrd, 0);
222 out_be32(&scm1->pacre, 0);
223 out_be32(&scm1->pacrf, 0);
224 out_be32(&scm1->pacrg, 0);
225
226 /* FlexBus */
227 out_8(&gpio->par_be,
228 GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 |
229 GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0);
230 out_8(&gpio->par_fbctl,
231 GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA |
232 GPIO_PAR_FBCTL_RW_RW | GPIO_PAR_FBCTL_TS_TS);
233
234 #ifdef CONFIG_CF_SPI
235 cfspi_port_conf();
236 #endif
237
238 #ifdef CONFIG_SYS_FSL_I2C
239 out_be16(&gpio->par_feci2c,
240 GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA);
241 #endif
242 #endif /* CONFIG_MCF5445x */
243
244 /* FlexBus Chipselect */
245 init_fbcs();
246
247 #ifdef CONFIG_SYS_CS0_BASE
248 /*
249 * now the flash base address is no longer at 0 (Newer ColdFire family
250 * boot at address 0 instead of 0xFFnn_nnnn). The vector table must
251 * also move to the new location.
252 */
253 if (CONFIG_SYS_CS0_BASE != 0)
254 setvbr(CONFIG_SYS_CS0_BASE);
255 #endif
256
257 icache_enable();
258 }
259
260 /*
261 * initialize higher level parts of CPU like timers
262 */
cpu_init_r(void)263 int cpu_init_r(void)
264 {
265 #ifdef CONFIG_MCFRTC
266 rtc_t *rtc = (rtc_t *)(CONFIG_SYS_MCFRTC_BASE);
267 rtcex_t *rtcex = (rtcex_t *)&rtc->extended;
268
269 out_be32(&rtcex->gocu, (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xffff);
270 out_be32(&rtcex->gocl, CONFIG_SYS_RTC_OSCILLATOR & 0xffff);
271 #endif
272
273 return (0);
274 }
275
uart_port_conf(int port)276 void uart_port_conf(int port)
277 {
278 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
279 #ifdef CONFIG_MCF5441x
280 pm_t *pm = (pm_t *) MMAP_PM;
281 #endif
282
283 /* Setup Ports: */
284 switch (port) {
285 #ifdef CONFIG_MCF5441x
286 case 0:
287 /* UART0 */
288 out_8(&pm->pmcr0, 24);
289 clrbits_8(&gpio->par_uart0,
290 ~(GPIO_PAR_UART0_U0RXD_MASK | GPIO_PAR_UART0_U0TXD_MASK));
291 setbits_8(&gpio->par_uart0,
292 GPIO_PAR_UART0_U0RXD_U0RXD | GPIO_PAR_UART0_U0TXD_U0TXD);
293 break;
294 case 1:
295 /* UART1 */
296 out_8(&pm->pmcr0, 25);
297 clrbits_8(&gpio->par_uart1,
298 ~(GPIO_PAR_UART1_U1RXD_MASK | GPIO_PAR_UART1_U1TXD_MASK));
299 setbits_8(&gpio->par_uart1,
300 GPIO_PAR_UART1_U1RXD_U1RXD | GPIO_PAR_UART1_U1TXD_U1TXD);
301 break;
302 case 2:
303 /* UART2 */
304 out_8(&pm->pmcr0, 26);
305 clrbits_8(&gpio->par_uart2,
306 ~(GPIO_PAR_UART2_U2RXD_MASK | GPIO_PAR_UART2_U2TXD_MASK));
307 setbits_8(&gpio->par_uart2,
308 GPIO_PAR_UART2_U2RXD_U2RXD | GPIO_PAR_UART2_U2TXD_U2TXD);
309 break;
310 case 3:
311 /* UART3 */
312 out_8(&pm->pmcr0, 27);
313 clrbits_8(&gpio->par_dspi0,
314 ~(GPIO_PAR_DSPI0_SIN_MASK | GPIO_PAR_DSPI0_SOUT_MASK));
315 setbits_8(&gpio->par_dspi0,
316 GPIO_PAR_DSPI0_SIN_U3RXD | GPIO_PAR_DSPI0_SOUT_U3TXD);
317 break;
318 case 4:
319 /* UART4 */
320 out_8(&pm->pmcr1, 24);
321 clrbits_8(&gpio->par_uart0,
322 ~(GPIO_PAR_UART0_U0CTS_MASK | GPIO_PAR_UART0_U0RTS_MASK));
323 setbits_8(&gpio->par_uart0,
324 GPIO_PAR_UART0_U0CTS_U4TXD | GPIO_PAR_UART0_U0RTS_U4RXD);
325 break;
326 case 5:
327 /* UART5 */
328 out_8(&pm->pmcr1, 25);
329 clrbits_8(&gpio->par_uart1,
330 ~(GPIO_PAR_UART1_U1CTS_MASK | GPIO_PAR_UART1_U1RTS_MASK));
331 setbits_8(&gpio->par_uart1,
332 GPIO_PAR_UART1_U1CTS_U5TXD | GPIO_PAR_UART1_U1RTS_U5RXD);
333 break;
334 case 6:
335 /* UART6 */
336 out_8(&pm->pmcr1, 26);
337 clrbits_8(&gpio->par_uart2,
338 ~(GPIO_PAR_UART2_U2CTS_MASK | GPIO_PAR_UART2_U2RTS_MASK));
339 setbits_8(&gpio->par_uart2,
340 GPIO_PAR_UART2_U2CTS_U6TXD | GPIO_PAR_UART2_U2RTS_U6RXD);
341 break;
342 case 7:
343 /* UART7 */
344 out_8(&pm->pmcr1, 27);
345 clrbits_8(&gpio->par_ssi0h, ~GPIO_PAR_SSI0H_RXD_MASK);
346 clrbits_8(&gpio->par_ssi0l, ~GPIO_PAR_SSI0L_BCLK_MASK);
347 setbits_8(&gpio->par_ssi0h, GPIO_PAR_SSI0H_FS_U7TXD);
348 setbits_8(&gpio->par_ssi0l, GPIO_PAR_SSI0L_BCLK_U7RXD);
349 break;
350 case 8:
351 /* UART8 */
352 out_8(&pm->pmcr0, 28);
353 clrbits_8(&gpio->par_cani2c,
354 ~(GPIO_PAR_CANI2C_I2C0SCL_MASK | GPIO_PAR_CANI2C_I2C0SDA_MASK));
355 setbits_8(&gpio->par_cani2c,
356 GPIO_PAR_CANI2C_I2C0SCL_U8TXD | GPIO_PAR_CANI2C_I2C0SDA_U8RXD);
357 break;
358 case 9:
359 /* UART9 */
360 out_8(&pm->pmcr1, 29);
361 clrbits_8(&gpio->par_cani2c,
362 ~(GPIO_PAR_CANI2C_CAN1TX_MASK | GPIO_PAR_CANI2C_CAN1RX_MASK));
363 setbits_8(&gpio->par_cani2c,
364 GPIO_PAR_CANI2C_CAN1TX_U9TXD | GPIO_PAR_CANI2C_CAN1RX_U9RXD);
365 break;
366 #endif
367 #ifdef CONFIG_MCF5445x
368 case 0:
369 clrbits_8(&gpio->par_uart,
370 GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
371 setbits_8(&gpio->par_uart,
372 GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
373 break;
374 case 1:
375 #ifdef CONFIG_SYS_UART1_PRI_GPIO
376 clrbits_8(&gpio->par_uart,
377 GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
378 setbits_8(&gpio->par_uart,
379 GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
380 #elif defined(CONFIG_SYS_UART1_ALT1_GPIO)
381 clrbits_be16(&gpio->par_ssi,
382 ~(GPIO_PAR_SSI_SRXD_UNMASK | GPIO_PAR_SSI_STXD_UNMASK));
383 setbits_be16(&gpio->par_ssi,
384 GPIO_PAR_SSI_SRXD_U1RXD | GPIO_PAR_SSI_STXD_U1TXD);
385 #endif
386 break;
387 case 2:
388 #if defined(CONFIG_SYS_UART2_ALT1_GPIO)
389 clrbits_8(&gpio->par_timer,
390 ~(GPIO_PAR_TIMER_T3IN_UNMASK | GPIO_PAR_TIMER_T2IN_UNMASK));
391 setbits_8(&gpio->par_timer,
392 GPIO_PAR_TIMER_T3IN_U2RXD | GPIO_PAR_TIMER_T2IN_U2TXD);
393 #elif defined(CONFIG_SYS_UART2_ALT2_GPIO)
394 clrbits_8(&gpio->par_timer,
395 ~(GPIO_PAR_FECI2C_SCL_UNMASK | GPIO_PAR_FECI2C_SDA_UNMASK));
396 setbits_8(&gpio->par_timer,
397 GPIO_PAR_FECI2C_SCL_U2TXD | GPIO_PAR_FECI2C_SDA_U2RXD);
398 #endif
399 break;
400 #endif /* CONFIG_MCF5445x */
401 }
402 }
403
404 #if defined(CONFIG_CMD_NET)
fecpin_setclear(struct eth_device * dev,int setclear)405 int fecpin_setclear(struct eth_device *dev, int setclear)
406 {
407 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
408 #ifdef CONFIG_MCF5445x
409 struct fec_info_s *info = (struct fec_info_s *)dev->priv;
410
411 if (setclear) {
412 #ifdef CONFIG_SYS_FEC_NO_SHARED_PHY
413 if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
414 setbits_be16(&gpio->par_feci2c,
415 GPIO_PAR_FECI2C_MDC0_MDC0 |
416 GPIO_PAR_FECI2C_MDIO0_MDIO0);
417 else
418 setbits_be16(&gpio->par_feci2c,
419 GPIO_PAR_FECI2C_MDC1_MDC1 |
420 GPIO_PAR_FECI2C_MDIO1_MDIO1);
421 #else
422 setbits_be16(&gpio->par_feci2c,
423 GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
424 #endif
425
426 if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
427 setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC0_RMII_GPIO);
428 else
429 setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC1_RMII_ATA);
430 } else {
431 clrbits_be16(&gpio->par_feci2c,
432 GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
433
434 if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
435 #ifdef CONFIG_SYS_FEC_FULL_MII
436 setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC0_MII);
437 #else
438 clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC0_UNMASK);
439 #endif
440 } else {
441 #ifdef CONFIG_SYS_FEC_FULL_MII
442 setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC1_MII);
443 #else
444 clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC1_UNMASK);
445 #endif
446 }
447 }
448 #endif /* CONFIG_MCF5445x */
449
450 #ifdef CONFIG_MCF5441x
451 if (setclear) {
452 out_8(&gpio->par_fec, 0x03);
453 out_8(&gpio->srcr_fec, 0x0F);
454 clrsetbits_8(&gpio->par_simp0h, ~GPIO_PAR_SIMP0H_DAT_MASK,
455 GPIO_PAR_SIMP0H_DAT_GPIO);
456 clrsetbits_8(&gpio->pddr_g, ~GPIO_PDDR_G4_MASK,
457 GPIO_PDDR_G4_OUTPUT);
458 clrbits_8(&gpio->podr_g, ~GPIO_PODR_G4_MASK);
459
460 } else
461 clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC_MASK);
462 #endif
463 return 0;
464 }
465 #endif
466
467