1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
4 *
5 * (C) Copyright 2000
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 */
8
9 #include <common.h>
10 #include <irq_func.h>
11 #include <time.h>
12
13 #include <asm/timer.h>
14 #include <asm/immap.h>
15 #include <watchdog.h>
16
17 DECLARE_GLOBAL_DATA_PTR;
18
19 static volatile ulong timestamp = 0;
20
21 #ifndef CONFIG_SYS_WATCHDOG_FREQ
22 #define CONFIG_SYS_WATCHDOG_FREQ (CONFIG_SYS_HZ / 2)
23 #endif
24
25 #if defined(CONFIG_MCFTMR)
26 #ifndef CONFIG_SYS_UDELAY_BASE
27 # error "uDelay base not defined!"
28 #endif
29
30 #if !defined(CONFIG_SYS_TMR_BASE) || !defined(CONFIG_SYS_INTR_BASE) || !defined(CONFIG_SYS_TMRINTR_NO) || !defined(CONFIG_SYS_TMRINTR_MASK)
31 # error "TMR_BASE, INTR_BASE, TMRINTR_NO or TMRINTR_MASk not defined!"
32 #endif
33 extern void dtimer_intr_setup(void);
34
__udelay(unsigned long usec)35 void __udelay(unsigned long usec)
36 {
37 volatile dtmr_t *timerp = (dtmr_t *) (CONFIG_SYS_UDELAY_BASE);
38 uint start, now, tmp;
39
40 while (usec > 0) {
41 if (usec > 65000)
42 tmp = 65000;
43 else
44 tmp = usec;
45 usec = usec - tmp;
46
47 /* Set up TIMER 3 as timebase clock */
48 timerp->tmr = DTIM_DTMR_RST_RST;
49 timerp->tcn = 0;
50 /* set period to 1 us */
51 timerp->tmr =
52 CONFIG_SYS_TIMER_PRESCALER | DTIM_DTMR_CLK_DIV1 | DTIM_DTMR_FRR |
53 DTIM_DTMR_RST_EN;
54
55 start = now = timerp->tcn;
56 while (now < start + tmp)
57 now = timerp->tcn;
58 }
59 }
60
dtimer_interrupt(void * not_used)61 void dtimer_interrupt(void *not_used)
62 {
63 volatile dtmr_t *timerp = (dtmr_t *) (CONFIG_SYS_TMR_BASE);
64
65 /* check for timer interrupt asserted */
66 if ((CONFIG_SYS_TMRPND_REG & CONFIG_SYS_TMRINTR_MASK) == CONFIG_SYS_TMRINTR_PEND) {
67 timerp->ter = (DTIM_DTER_CAP | DTIM_DTER_REF);
68 timestamp++;
69
70 #if defined(CONFIG_WATCHDOG) || defined (CONFIG_HW_WATCHDOG)
71 if ((timestamp % (CONFIG_SYS_WATCHDOG_FREQ)) == 0) {
72 WATCHDOG_RESET ();
73 }
74 #endif /* CONFIG_WATCHDOG || CONFIG_HW_WATCHDOG */
75 return;
76 }
77 }
78
timer_init(void)79 int timer_init(void)
80 {
81 volatile dtmr_t *timerp = (dtmr_t *) (CONFIG_SYS_TMR_BASE);
82
83 timestamp = 0;
84
85 timerp->tcn = 0;
86 timerp->trr = 0;
87
88 /* Set up TIMER 4 as clock */
89 timerp->tmr = DTIM_DTMR_RST_RST;
90
91 /* initialize and enable timer interrupt */
92 irq_install_handler(CONFIG_SYS_TMRINTR_NO, dtimer_interrupt, 0);
93
94 timerp->tcn = 0;
95 timerp->trr = 1000; /* Interrupt every ms */
96
97 dtimer_intr_setup();
98
99 /* set a period of 1us, set timer mode to restart and enable timer and interrupt */
100 timerp->tmr = CONFIG_SYS_TIMER_PRESCALER | DTIM_DTMR_CLK_DIV1 |
101 DTIM_DTMR_FRR | DTIM_DTMR_ORRI | DTIM_DTMR_RST_EN;
102
103 return 0;
104 }
105
get_timer(ulong base)106 ulong get_timer(ulong base)
107 {
108 return (timestamp - base);
109 }
110
111 #endif /* CONFIG_MCFTMR */
112
113 #if defined(CONFIG_MCFPIT)
114 #if !defined(CONFIG_SYS_PIT_BASE)
115 # error "CONFIG_SYS_PIT_BASE not defined!"
116 #endif
117
118 static unsigned short lastinc;
119
__udelay(unsigned long usec)120 void __udelay(unsigned long usec)
121 {
122 volatile pit_t *timerp = (pit_t *) (CONFIG_SYS_UDELAY_BASE);
123 uint tmp;
124
125 while (usec > 0) {
126 if (usec > 65000)
127 tmp = 65000;
128 else
129 tmp = usec;
130 usec = usec - tmp;
131
132 /* Set up TIMER 3 as timebase clock */
133 timerp->pcsr = PIT_PCSR_OVW;
134 timerp->pmr = 0;
135 /* set period to 1 us */
136 timerp->pcsr |= PIT_PCSR_PRE(CONFIG_SYS_PIT_PRESCALE) | PIT_PCSR_EN;
137
138 timerp->pmr = tmp;
139 while (timerp->pcntr > 0) ;
140 }
141 }
142
timer_init(void)143 void timer_init(void)
144 {
145 volatile pit_t *timerp = (pit_t *) (CONFIG_SYS_PIT_BASE);
146 timestamp = 0;
147
148 /* Set up TIMER 4 as poll clock */
149 timerp->pcsr = PIT_PCSR_OVW;
150 timerp->pmr = lastinc = 0;
151 timerp->pcsr |= PIT_PCSR_PRE(CONFIG_SYS_PIT_PRESCALE) | PIT_PCSR_EN;
152
153 return 0;
154 }
155
get_timer(ulong base)156 ulong get_timer(ulong base)
157 {
158 unsigned short now, diff;
159 volatile pit_t *timerp = (pit_t *) (CONFIG_SYS_PIT_BASE);
160
161 now = timerp->pcntr;
162 diff = -(now - lastinc);
163
164 timestamp += diff;
165 lastinc = now;
166 return timestamp - base;
167 }
168
wait_ticks(unsigned long ticks)169 void wait_ticks(unsigned long ticks)
170 {
171 u32 start = get_timer(0);
172 while (get_timer(start) < ticks) ;
173 }
174 #endif /* CONFIG_MCFPIT */
175
176 /*
177 * This function is derived from PowerPC code (read timebase as long long).
178 * On M68K it just returns the timer value.
179 */
get_ticks(void)180 unsigned long long get_ticks(void)
181 {
182 return get_timer(0);
183 }
184
usec2ticks(unsigned long usec)185 unsigned long usec2ticks(unsigned long usec)
186 {
187 return get_timer(usec);
188 }
189
190 /*
191 * This function is derived from PowerPC code (timebase clock frequency).
192 * On M68K it returns the number of timer ticks per second.
193 */
get_tbclk(void)194 ulong get_tbclk(void)
195 {
196 return CONFIG_SYS_HZ;
197 }
198