1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 4 */ 5 6 #include <common.h> 7 #include <mpc83xx.h> 8 9 #include "lblaw/lblaw.h" 10 #include "elbc/elbc.h" 11 12 DECLARE_GLOBAL_DATA_PTR; 13 14 /* 15 * Breathe some life into the CPU... 16 * 17 * Set up the memory map, 18 * initialize a bunch of registers, 19 * initialize the UPM's 20 */ cpu_init_f(volatile immap_t * im)21void cpu_init_f (volatile immap_t * im) 22 { 23 /* Pointer is writable since we allocated a register for it */ 24 gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); 25 26 /* global data region was cleared in start.S */ 27 28 /* system performance tweaking */ 29 30 #ifndef CONFIG_ACR_PIPE_DEP_UNSET 31 /* Arbiter pipeline depth */ 32 im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) | 33 CONFIG_ACR_PIPE_DEP; 34 #endif 35 36 #ifndef CONFIG_ACR_RPTCNT_UNSET 37 /* Arbiter repeat count */ 38 im->arbiter.acr = (im->arbiter.acr & ~(ACR_RPTCNT)) | 39 CONFIG_ACR_RPTCNT; 40 #endif 41 42 #ifdef CONFIG_SYS_SPCR_OPT 43 /* Optimize transactions between CSB and other devices */ 44 im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_OPT) | 45 (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT); 46 #endif 47 48 /* Enable Time Base & Decrementer (so we will have udelay()) */ 49 im->sysconf.spcr |= SPCR_TBEN; 50 51 /* DDR control driver register */ 52 #ifdef CONFIG_SYS_DDRCDR 53 im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR; 54 #endif 55 /* Output buffer impedance register */ 56 #ifdef CONFIG_SYS_OBIR 57 im->sysconf.obir = CONFIG_SYS_OBIR; 58 #endif 59 60 /* 61 * Memory Controller: 62 */ 63 64 /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary 65 * addresses - these have to be modified later when FLASH size 66 * has been determined 67 */ 68 69 #if defined(CONFIG_SYS_NAND_BR_PRELIM) \ 70 && defined(CONFIG_SYS_NAND_OR_PRELIM) \ 71 && defined(CONFIG_SYS_NAND_LBLAWBAR_PRELIM) \ 72 && defined(CONFIG_SYS_NAND_LBLAWAR_PRELIM) 73 set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM); 74 set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM); 75 im->sysconf.lblaw[0].bar = CONFIG_SYS_NAND_LBLAWBAR_PRELIM; 76 im->sysconf.lblaw[0].ar = CONFIG_SYS_NAND_LBLAWAR_PRELIM; 77 #else 78 #error CONFIG_SYS_NAND_BR_PRELIM, CONFIG_SYS_NAND_OR_PRELIM, CONFIG_SYS_NAND_LBLAWBAR_PRELIM & CONFIG_SYS_NAND_LBLAWAR_PRELIM must be defined 79 #endif 80 } 81 82 /* 83 * Get timebase clock frequency (like cpu_clk in Hz) 84 */ get_tbclk(void)85unsigned long get_tbclk(void) 86 { 87 return (gd->bus_clk + 3L) / 4L; 88 } 89 puts(const char * str)90void puts(const char *str) 91 { 92 while (*str) 93 putc(*str++); 94 } 95 get_bus_freq(ulong dummy)96ulong get_bus_freq(ulong dummy) 97 { 98 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; 99 u8 spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT; 100 101 return CONFIG_SYS_CLK_FREQ * spmf; 102 } 103