1// SPDX-License-Identifier: GPL-2.0+ OR X11 2/* 3 * P1020 Silicon/SoC Device Tree Source (post include) 4 * 5 * Copyright 2013 Freescale Semiconductor Inc. 6 * Copyright 2019 NXP 7 */ 8 9&soc { 10 #address-cells = <1>; 11 #size-cells = <1>; 12 device_type = "soc"; 13 compatible = "fsl,p1020-immr", "simple-bus"; 14 bus-frequency = <0x0>; 15 16 mpic: pic@40000 { 17 interrupt-controller; 18 #address-cells = <0>; 19 #interrupt-cells = <4>; 20 reg = <0x40000 0x40000>; 21 compatible = "fsl,mpic"; 22 device_type = "open-pic"; 23 big-endian; 24 single-cpu-affinity; 25 last-interrupt-source = <255>; 26 }; 27 28 esdhc: esdhc@2e000 { 29 compatible = "fsl,esdhc"; 30 reg = <0x2e000 0x1000>; 31 /* Filled in by U-Boot */ 32 clock-frequency = <0>; 33 }; 34}; 35 36/* PCIe controller base address 0x9000 */ 37&pci1 { 38 compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq"; 39 law_trgt_if = <1>; 40 #address-cells = <3>; 41 #size-cells = <2>; 42 device_type = "pci"; 43 bus-range = <0x0 0xff>; 44}; 45 46/* PCIe controller base address 0xa000 */ 47&pci0 { 48 compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq"; 49 law_trgt_if = <2>; 50 #address-cells = <3>; 51 #size-cells = <2>; 52 device_type = "pci"; 53 bus-range = <0x0 0xff>; 54}; 55