1// SPDX-License-Identifier: GPL-2.0+ OR X11 2/* 3 * T2080/T2081 Silicon/SoC Device Tree Source (pre include) 4 * 5 * Copyright 2013 Freescale Semiconductor Inc. 6 * Copyright 2018 NXP 7 */ 8 9/dts-v1/; 10 11/include/ "e6500_power_isa.dtsi" 12 13/ { 14 #address-cells = <2>; 15 #size-cells = <2>; 16 interrupt-parent = <&mpic>; 17 18 cpus { 19 #address-cells = <1>; 20 #size-cells = <0>; 21 22 cpu0: PowerPC,e6500@0 { 23 device_type = "cpu"; 24 reg = <0 1>; 25 fsl,portid-mapping = <0x80000000>; 26 }; 27 cpu1: PowerPC,e6500@2 { 28 device_type = "cpu"; 29 reg = <2 3>; 30 fsl,portid-mapping = <0x80000000>; 31 }; 32 cpu2: PowerPC,e6500@4 { 33 device_type = "cpu"; 34 reg = <4 5>; 35 fsl,portid-mapping = <0x80000000>; 36 }; 37 cpu3: PowerPC,e6500@6 { 38 device_type = "cpu"; 39 reg = <6 7>; 40 fsl,portid-mapping = <0x80000000>; 41 }; 42 }; 43 44 soc: soc@ffe000000 { 45 ranges = <0x00000000 0xf 0xfe000000 0x1000000>; 46 reg = <0xf 0xfe000000 0 0x00001000>; 47 #address-cells = <1>; 48 #size-cells = <1>; 49 device_type = "soc"; 50 compatible = "simple-bus"; 51 52 mpic: pic@40000 { 53 interrupt-controller; 54 #address-cells = <0>; 55 #interrupt-cells = <4>; 56 reg = <0x40000 0x40000>; 57 compatible = "fsl,mpic"; 58 device_type = "open-pic"; 59 clock-frequency = <0x0>; 60 }; 61 62 esdhc: esdhc@114000 { 63 compatible = "fsl,esdhc"; 64 reg = <0x114000 0x1000>; 65 interrupts = <48 2 0 0>; 66 clock-frequency = <0>; 67 sdhci,auto-cmd12; 68 bus-width = <4>; 69 voltage-ranges = <1800 1800 3300 3300>; 70 }; 71 72 usb0: usb@210000 { 73 compatible = "fsl-usb2-mph"; 74 reg = <0x210000 0x1000>; 75 #address-cells = <1>; 76 #size-cells = <0>; 77 interrupts = <44 0x2 0 0>; 78 phy_type = "utmi"; 79 }; 80 81 usb1: usb@211000 { 82 compatible = "fsl-usb2-dr"; 83 reg = <0x211000 0x1000>; 84 #address-cells = <1>; 85 #size-cells = <0>; 86 interrupts = <45 0x2 0 0>; 87 dr_mode = "host"; 88 phy_type = "utmi"; 89 }; 90 91 sata0: sata@220000 { 92 compatible = "fsl,pq-sata-v2"; 93 reg = <0x220000 0x1000>; 94 interrupts = <68 0x2 0 0>; 95 sata-number = <0x0>; 96 sata-fpdma = <0x0>; 97 }; 98 99 sata1: sata@221000 { 100 compatible = "fsl,pq-sata-v2"; 101 reg = <0x221000 0x1000>; 102 interrupts = <69 0x2 0 0>; 103 sata-number = <0x0>; 104 sata-fpdma = <0x0>; 105 }; 106 }; 107 108 pcie@ffe240000 { 109 compatible = "fsl,pcie-t2080", "fsl,pcie-fsl-qoriq"; 110 reg = <0xf 0xfe240000 0x0 0x4000>; /* registers */ 111 law_trgt_if = <0>; 112 #address-cells = <3>; 113 #size-cells = <2>; 114 device_type = "pci"; 115 bus-range = <0x0 0xff>; 116 ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */ 117 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */ 118 }; 119 120 pcie@ffe250000 { 121 compatible = "fsl,pcie-t2080", "fsl,pcie-fsl-qoriq"; 122 reg = <0xf 0xfe250000 0x0 0x1000>; /* registers */ 123 law_trgt_if = <1>; 124 #address-cells = <3>; 125 #size-cells = <2>; 126 device_type = "pci"; 127 bus-range = <0x0 0xff>; 128 ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */ 129 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x10000000>; /* non-prefetchable memory */ 130 }; 131 132 pcie@ffe260000 { 133 compatible = "fsl,pcie-t2080", "fsl,pcie-fsl-qoriq"; 134 reg = <0xf 0xfe260000 0x0 0x1000>; /* registers */ 135 law_trgt_if = <2>; 136 #address-cells = <3>; 137 #size-cells = <2>; 138 device_type = "pci"; 139 bus-range = <0x0 0xff>; 140 ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */ 141 0x02000000 0x0 0xe0000000 0xc 0x30000000 0x0 0x10000000>; /* non-prefetchable memory */ 142 }; 143 144 pcie@ffe270000 { 145 compatible = "fsl,pcie-t2080", "fsl,pcie-fsl-qoriq"; 146 reg = <0xf 0xfe270000 0x0 0x1000>; /* registers */ 147 law_trgt_if = <3>; 148 #address-cells = <3>; 149 #size-cells = <2>; 150 device_type = "pci"; 151 bus-range = <0x0 0xff>; 152 ranges = <0x01000000 0x0 0x00000000 0xf 0xf8030000 0x0 0x00010000 /* downstream I/O */ 153 0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x10000000>; /* non-prefetchable memory */ 154 }; 155}; 156