1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
4 */
5
6 #include <common.h>
7 #include <cpu.h>
8 #include <dm.h>
9 #include <log.h>
10 #include <asm/encoding.h>
11 #include <dm/uclass-internal.h>
12
13 /*
14 * The variables here must be stored in the data section since they are used
15 * before the bss section is available.
16 */
17 #ifdef CONFIG_OF_PRIOR_STAGE
18 phys_addr_t prior_stage_fdt_address __attribute__((section(".data")));
19 #endif
20 #ifndef CONFIG_XIP
21 u32 hart_lottery __attribute__((section(".data"))) = 0;
22
23 /*
24 * The main hart running U-Boot has acquired available_harts_lock until it has
25 * finished initialization of global data.
26 */
27 u32 available_harts_lock = 1;
28 #endif
29
supports_extension(char ext)30 static inline bool supports_extension(char ext)
31 {
32 #ifdef CONFIG_CPU
33 struct udevice *dev;
34 char desc[32];
35
36 uclass_find_first_device(UCLASS_CPU, &dev);
37 if (!dev) {
38 debug("unable to find the RISC-V cpu device\n");
39 return false;
40 }
41 if (!cpu_get_desc(dev, desc, sizeof(desc))) {
42 /* skip the first 4 characters (rv32|rv64) */
43 if (strchr(desc + 4, ext))
44 return true;
45 }
46
47 return false;
48 #else /* !CONFIG_CPU */
49 #if CONFIG_IS_ENABLED(RISCV_MMODE)
50 return csr_read(CSR_MISA) & (1 << (ext - 'a'));
51 #else /* !CONFIG_IS_ENABLED(RISCV_MMODE) */
52 #warning "There is no way to determine the available extensions in S-mode."
53 #warning "Please convert your board to use the RISC-V CPU driver."
54 return false;
55 #endif /* CONFIG_IS_ENABLED(RISCV_MMODE) */
56 #endif /* CONFIG_CPU */
57 }
58
riscv_cpu_probe(void)59 static int riscv_cpu_probe(void)
60 {
61 #ifdef CONFIG_CPU
62 int ret;
63
64 /* probe cpus so that RISC-V timer can be bound */
65 ret = cpu_probe_all();
66 if (ret)
67 return log_msg_ret("RISC-V cpus probe failed\n", ret);
68 #endif
69
70 return 0;
71 }
72
arch_cpu_init_dm(void)73 int arch_cpu_init_dm(void)
74 {
75 int ret;
76
77 ret = riscv_cpu_probe();
78 if (ret)
79 return ret;
80
81 /* Enable FPU */
82 if (supports_extension('d') || supports_extension('f')) {
83 csr_set(MODE_PREFIX(status), MSTATUS_FS);
84 csr_write(CSR_FCSR, 0);
85 }
86
87 if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
88 /*
89 * Enable perf counters for cycle, time,
90 * and instret counters only
91 */
92 csr_write(CSR_MCOUNTEREN, GENMASK(2, 0));
93
94 /* Disable paging */
95 if (supports_extension('s'))
96 csr_write(CSR_SATP, 0);
97 }
98
99 return 0;
100 }
101
arch_early_init_r(void)102 int arch_early_init_r(void)
103 {
104 return riscv_cpu_probe();
105 }
106