1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2016 Vladimir Zapolskiy <vz@mleia.com>
4 * (C) Copyright 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
5 */
6
7 #include <common.h>
8 #include <command.h>
9 #include <cpu_func.h>
10 #include <asm/io.h>
11 #include <asm/processor.h>
12 #include <asm/system.h>
13
14 #define CACHE_VALID 1
15 #define CACHE_UPDATED 2
16
cache_wback_all(void)17 static inline void cache_wback_all(void)
18 {
19 unsigned long addr, data, i, j;
20
21 for (i = 0; i < CACHE_OC_NUM_ENTRIES; i++) {
22 for (j = 0; j < CACHE_OC_NUM_WAYS; j++) {
23 addr = CACHE_OC_ADDRESS_ARRAY
24 | (j << CACHE_OC_WAY_SHIFT)
25 | (i << CACHE_OC_ENTRY_SHIFT);
26 data = inl(addr);
27 if (data & CACHE_UPDATED) {
28 data &= ~CACHE_UPDATED;
29 outl(data, addr);
30 }
31 }
32 }
33 }
34
35 #define CACHE_ENABLE 0
36 #define CACHE_DISABLE 1
37
cache_control(unsigned int cmd)38 static int cache_control(unsigned int cmd)
39 {
40 unsigned long ccr;
41
42 jump_to_P2();
43 ccr = inl(CCR);
44
45 if (ccr & CCR_CACHE_ENABLE)
46 cache_wback_all();
47
48 if (cmd == CACHE_DISABLE)
49 outl(CCR_CACHE_STOP, CCR);
50 else
51 outl(CCR_CACHE_INIT, CCR);
52 back_to_P1();
53
54 return 0;
55 }
56
flush_dcache_range(unsigned long start,unsigned long end)57 void flush_dcache_range(unsigned long start, unsigned long end)
58 {
59 u32 v;
60
61 start &= ~(L1_CACHE_BYTES - 1);
62 for (v = start; v < end; v += L1_CACHE_BYTES) {
63 asm volatile ("ocbp %0" : /* no output */
64 : "m" (__m(v)));
65 }
66 }
67
invalidate_dcache_range(unsigned long start,unsigned long end)68 void invalidate_dcache_range(unsigned long start, unsigned long end)
69 {
70 u32 v;
71
72 start &= ~(L1_CACHE_BYTES - 1);
73 for (v = start; v < end; v += L1_CACHE_BYTES) {
74 asm volatile ("ocbi %0" : /* no output */
75 : "m" (__m(v)));
76 }
77 }
78
flush_cache(unsigned long addr,unsigned long size)79 void flush_cache(unsigned long addr, unsigned long size)
80 {
81 flush_dcache_range(addr , addr + size);
82 }
83
icache_enable(void)84 void icache_enable(void)
85 {
86 cache_control(CACHE_ENABLE);
87 }
88
icache_disable(void)89 void icache_disable(void)
90 {
91 cache_control(CACHE_DISABLE);
92 }
93
icache_status(void)94 int icache_status(void)
95 {
96 return 0;
97 }
98
dcache_enable(void)99 void dcache_enable(void)
100 {
101 }
102
dcache_disable(void)103 void dcache_disable(void)
104 {
105 }
106
dcache_status(void)107 int dcache_status(void)
108 {
109 return 0;
110 }
111