1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (c) 2011 The Chromium OS Authors. 4 * (C) Copyright 2008 5 * Graeme Russ, graeme.russ@gmail.com. 6 */ 7 8 #include <common.h> 9 #include <cpu_func.h> 10 #include <fdtdec.h> 11 #include <usb.h> 12 #include <asm/io.h> 13 #include <asm/msr.h> 14 #include <asm/mtrr.h> 15 #include <asm/arch/sysinfo.h> 16 #include <asm/arch/timestamp.h> 17 18 DECLARE_GLOBAL_DATA_PTR; 19 arch_cpu_init(void)20int arch_cpu_init(void) 21 { 22 int ret = get_coreboot_info(&lib_sysinfo); 23 if (ret != 0) { 24 printf("Failed to parse coreboot tables.\n"); 25 return ret; 26 } 27 28 timestamp_init(); 29 30 return x86_cpu_init_f(); 31 } 32 checkcpu(void)33int checkcpu(void) 34 { 35 return 0; 36 } 37 print_cpuinfo(void)38int print_cpuinfo(void) 39 { 40 return default_print_cpuinfo(); 41 } 42 board_final_cleanup(void)43static void board_final_cleanup(void) 44 { 45 /* 46 * Un-cache the ROM so the kernel has one 47 * more MTRR available. 48 * 49 * Coreboot should have assigned this to the 50 * top available variable MTRR. 51 */ 52 u8 top_mtrr = (native_read_msr(MTRR_CAP_MSR) & 0xff) - 1; 53 u8 top_type = native_read_msr(MTRR_PHYS_BASE_MSR(top_mtrr)) & 0xff; 54 55 /* Make sure this MTRR is the correct Write-Protected type */ 56 if (top_type == MTRR_TYPE_WRPROT) { 57 struct mtrr_state state; 58 59 mtrr_open(&state, true); 60 wrmsrl(MTRR_PHYS_BASE_MSR(top_mtrr), 0); 61 wrmsrl(MTRR_PHYS_MASK_MSR(top_mtrr), 0); 62 mtrr_close(&state, true); 63 } 64 65 if (!fdtdec_get_config_bool(gd->fdt_blob, "u-boot,no-apm-finalize")) { 66 /* 67 * Issue SMI to coreboot to lock down ME and registers 68 * when allowed via device tree 69 */ 70 printf("Finalizing coreboot\n"); 71 outb(0xcb, 0xb2); 72 } 73 } 74 last_stage_init(void)75int last_stage_init(void) 76 { 77 /* start usb so that usb keyboard can be used as input device */ 78 if (CONFIG_IS_ENABLED(USB_KEYBOARD)) 79 usb_init(); 80 81 board_final_cleanup(); 82 83 return 0; 84 } 85