1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
4 */
5
6 #include <common.h>
7 #include <cpu_func.h>
8 #include <errno.h>
9 #include <fdtdec.h>
10 #include <init.h>
11 #include <malloc.h>
12 #include <asm/mrccache.h>
13 #include <asm/mtrr.h>
14 #include <asm/post.h>
15 #include <asm/arch/mrc.h>
16 #include <asm/arch/msg_port.h>
17 #include <asm/arch/quark.h>
18
19 DECLARE_GLOBAL_DATA_PTR;
20
prepare_mrc_cache(struct mrc_params * mrc_params)21 static __maybe_unused int prepare_mrc_cache(struct mrc_params *mrc_params)
22 {
23 struct mrc_data_container *cache;
24 struct mrc_region entry;
25 int ret;
26
27 ret = mrccache_get_region(NULL, &entry);
28 if (ret)
29 return ret;
30
31 cache = mrccache_find_current(&entry);
32 if (!cache)
33 return -ENOENT;
34
35 debug("%s: mrc cache at %p, size %x checksum %04x\n", __func__,
36 cache->data, cache->data_size, cache->checksum);
37
38 /* copy mrc cache to the mrc_params */
39 memcpy(&mrc_params->timings, cache->data, cache->data_size);
40
41 return 0;
42 }
43
mrc_configure_params(struct mrc_params * mrc_params)44 static int mrc_configure_params(struct mrc_params *mrc_params)
45 {
46 const void *blob = gd->fdt_blob;
47 int node;
48 int mrc_flags;
49
50 node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_QRK_MRC);
51 if (node < 0) {
52 debug("%s: Cannot find MRC node\n", __func__);
53 return -EINVAL;
54 }
55
56 #ifdef CONFIG_ENABLE_MRC_CACHE
57 mrc_params->boot_mode = prepare_mrc_cache(mrc_params);
58 if (mrc_params->boot_mode)
59 mrc_params->boot_mode = BM_COLD;
60 else
61 mrc_params->boot_mode = BM_FAST;
62 #else
63 mrc_params->boot_mode = BM_COLD;
64 #endif
65
66 /*
67 * TODO:
68 *
69 * We need determine ECC by pin strap state
70 *
71 * Disable ECC by default for now
72 */
73 mrc_params->ecc_enables = 0;
74
75 mrc_flags = fdtdec_get_int(blob, node, "flags", 0);
76 if (mrc_flags & MRC_FLAG_SCRAMBLE_EN)
77 mrc_params->scrambling_enables = 1;
78 else
79 mrc_params->scrambling_enables = 0;
80
81 mrc_params->dram_width = fdtdec_get_int(blob, node, "dram-width", 0);
82 mrc_params->ddr_speed = fdtdec_get_int(blob, node, "dram-speed", 0);
83 mrc_params->ddr_type = fdtdec_get_int(blob, node, "dram-type", 0);
84
85 mrc_params->rank_enables = fdtdec_get_int(blob, node, "rank-mask", 0);
86 mrc_params->channel_enables = fdtdec_get_int(blob, node,
87 "chan-mask", 0);
88 mrc_params->channel_width = fdtdec_get_int(blob, node,
89 "chan-width", 0);
90 mrc_params->address_mode = fdtdec_get_int(blob, node, "addr-mode", 0);
91
92 mrc_params->refresh_rate = fdtdec_get_int(blob, node,
93 "refresh-rate", 0);
94 mrc_params->sr_temp_range = fdtdec_get_int(blob, node,
95 "sr-temp-range", 0);
96 mrc_params->ron_value = fdtdec_get_int(blob, node,
97 "ron-value", 0);
98 mrc_params->rtt_nom_value = fdtdec_get_int(blob, node,
99 "rtt-nom-value", 0);
100 mrc_params->rd_odt_value = fdtdec_get_int(blob, node,
101 "rd-odt-value", 0);
102
103 mrc_params->params.density = fdtdec_get_int(blob, node,
104 "dram-density", 0);
105 mrc_params->params.cl = fdtdec_get_int(blob, node, "dram-cl", 0);
106 mrc_params->params.ras = fdtdec_get_int(blob, node, "dram-ras", 0);
107 mrc_params->params.wtr = fdtdec_get_int(blob, node, "dram-wtr", 0);
108 mrc_params->params.rrd = fdtdec_get_int(blob, node, "dram-rrd", 0);
109 mrc_params->params.faw = fdtdec_get_int(blob, node, "dram-faw", 0);
110
111 debug("MRC dram_width %d\n", mrc_params->dram_width);
112 debug("MRC rank_enables %d\n", mrc_params->rank_enables);
113 debug("MRC ddr_speed %d\n", mrc_params->ddr_speed);
114 debug("MRC flags: %s\n",
115 (mrc_params->scrambling_enables) ? "SCRAMBLE_EN" : "");
116
117 debug("MRC density=%d tCL=%d tRAS=%d tWTR=%d tRRD=%d tFAW=%d\n",
118 mrc_params->params.density, mrc_params->params.cl,
119 mrc_params->params.ras, mrc_params->params.wtr,
120 mrc_params->params.rrd, mrc_params->params.faw);
121
122 return 0;
123 }
124
dram_init(void)125 int dram_init(void)
126 {
127 struct mrc_params mrc_params;
128 #ifdef CONFIG_ENABLE_MRC_CACHE
129 char *cache;
130 #endif
131 int ret;
132
133 memset(&mrc_params, 0, sizeof(struct mrc_params));
134 ret = mrc_configure_params(&mrc_params);
135 if (ret)
136 return ret;
137
138 /* Set up the DRAM by calling the memory reference code */
139 mrc_init(&mrc_params);
140 if (mrc_params.status)
141 return -EIO;
142
143 gd->ram_size = mrc_params.mem_size;
144 post_code(POST_DRAM);
145
146 /* variable range MTRR#2: RAM area */
147 disable_caches();
148 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_RAM),
149 0 | MTRR_TYPE_WRBACK);
150 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYMASK(MTRR_VAR_RAM),
151 (~(gd->ram_size - 1)) | MTRR_PHYS_MASK_VALID);
152 enable_caches();
153
154 #ifdef CONFIG_ENABLE_MRC_CACHE
155 cache = malloc(sizeof(struct mrc_timings));
156 if (cache) {
157 memcpy(cache, &mrc_params.timings, sizeof(struct mrc_timings));
158 gd->arch.mrc_output = cache;
159 gd->arch.mrc_output_len = sizeof(struct mrc_timings);
160 }
161 #endif
162
163 return 0;
164 }
165
dram_init_banksize(void)166 int dram_init_banksize(void)
167 {
168 gd->bd->bi_dram[0].start = 0;
169 gd->bd->bi_dram[0].size = gd->ram_size;
170
171 return 0;
172 }
173
174 /*
175 * This function looks for the highest region of memory lower than 4GB which
176 * has enough space for U-Boot where U-Boot is aligned on a page boundary.
177 * It overrides the default implementation found elsewhere which simply
178 * picks the end of ram, wherever that may be. The location of the stack,
179 * the relocation address, and how far U-Boot is moved by relocation are
180 * set in the global data structure.
181 */
board_get_usable_ram_top(ulong total_size)182 ulong board_get_usable_ram_top(ulong total_size)
183 {
184 return gd->ram_size;
185 }
186