1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Common code for Intel CPUs 4 * 5 * Copyright (c) 2016 Google, Inc 6 */ 7 8 #ifndef __ASM_CPU_COMMON_H 9 #define __ASM_CPU_COMMON_H 10 11 /* Standard Intel bus clock is fixed at 100MHz */ 12 enum { 13 INTEL_BCLK_MHZ = 100 14 }; 15 16 struct cpu_info; 17 18 /** 19 * cpu_common_init() - Set up common CPU init 20 * 21 * This reports BIST failure, enables the LAPIC, updates microcode, enables 22 * the upper 128-bytes of CROM RAM, probes the northbridge, PCH, LPC and SATA. 23 * 24 * @return 0 if OK, -ve on error 25 */ 26 int cpu_common_init(void); 27 28 /** 29 * cpu_set_flex_ratio_to_tdp_nominal() - Set up the maximum non-turbo rate 30 * 31 * If a change is needed, this function will do a soft reset so it takes 32 * effect. 33 * 34 * Some details are available here: 35 * http://forum.hwbot.org/showthread.php?t=76092 36 * 37 * @return 0 if OK, -ve on error 38 */ 39 int cpu_set_flex_ratio_to_tdp_nominal(void); 40 41 /** 42 * cpu_intel_get_info() - Obtain CPU info for Intel CPUs 43 * 44 * Most Intel CPUs use the same MSR to obtain the clock speed, and use the same 45 * features. This function fills in these values, given the value of the base 46 * clock in MHz (typically this should be set to 100). 47 * 48 * @info: cpu_info struct to fill in 49 * @bclk_mz: the base clock in MHz 50 * 51 * @return 0 always 52 */ 53 int cpu_intel_get_info(struct cpu_info *info, int bclk_mz); 54 55 /** 56 * cpu_configure_thermal_target() - Set the thermal target for a CPU 57 * 58 * This looks up the tcc-offset property and uses it to set the 59 * MSR_TEMPERATURE_TARGET value. 60 * 61 * @dev: CPU device 62 * @return 0 if OK, -ENOENT if no target is given in device tree 63 */ 64 int cpu_configure_thermal_target(struct udevice *dev); 65 66 /** 67 * cpu_set_perf_control() - Set the nominal CPU clock speed 68 * 69 * This sets the clock speed as a multiplier of BCLK 70 * 71 * @clk_ratio: Ratio to use 72 */ 73 void cpu_set_perf_control(uint clk_ratio); 74 75 /** 76 * cpu_config_tdp_levels() - Check for configurable TDP option 77 * 78 * @return true if the CPU has configurable TDP (Thermal-design power) 79 */ 80 bool cpu_config_tdp_levels(void); 81 82 /** enum burst_mode_t - Burst-mode states */ 83 enum burst_mode_t { 84 BURST_MODE_UNKNOWN, 85 BURST_MODE_UNAVAILABLE, 86 BURST_MODE_DISABLED, 87 BURST_MODE_ENABLED 88 }; 89 90 /* 91 * cpu_get_burst_mode_state() - Get the Burst/Turbo Mode State 92 * 93 * This reads MSR IA32_MISC_ENABLE 0x1A0 94 * Bit 38 - TURBO_MODE_DISABLE Bit to get state ENABLED / DISABLED. 95 * Also checks cpuid 0x6 to see whether burst mode is supported. 96 * 97 * @return current burst mode status 98 */ 99 enum burst_mode_t cpu_get_burst_mode_state(void); 100 101 /** 102 * cpu_set_burst_mode() - Set CPU burst mode 103 * 104 * @burst_mode: true to enable burst mode, false to disable 105 */ 106 void cpu_set_burst_mode(bool burst_mode); 107 108 /** 109 * cpu_set_eist() - Enable Enhanced Intel Speed Step Technology 110 * 111 * @eist_status: true to enable EIST, false to disable 112 */ 113 void cpu_set_eist(bool eist_status); 114 115 /** 116 * cpu_set_p_state_to_turbo_ratio() - Set turbo ratio 117 * 118 * TURBO_RATIO_LIMIT MSR (0x1AD) Bits 31:0 indicates the 119 * factory configured values for of 1-core, 2-core, 3-core 120 * and 4-core turbo ratio limits for all processors. 121 * 122 * 7:0 - MAX_TURBO_1_CORE 123 * 15:8 - MAX_TURBO_2_CORES 124 * 23:16 - MAX_TURBO_3_CORES 125 * 31:24 - MAX_TURBO_4_CORES 126 * 127 * Set PERF_CTL MSR (0x199) P_Req with that value. 128 */ 129 void cpu_set_p_state_to_turbo_ratio(void); 130 131 #endif 132