1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2018 Google, Inc
4 */
5
6 #include <common.h>
7 #include <debug_uart.h>
8 #include <dm.h>
9 #include <spl.h>
10 #include <asm/cpu.h>
11 #include <asm/mtrr.h>
12 #include <asm/processor.h>
13 #include <asm-generic/sections.h>
14
15 DECLARE_GLOBAL_DATA_PTR;
16
arch_cpu_init_dm(void)17 __weak int arch_cpu_init_dm(void)
18 {
19 return 0;
20 }
21
x86_tpl_init(void)22 static int x86_tpl_init(void)
23 {
24 int ret;
25
26 debug("%s starting\n", __func__);
27 ret = x86_cpu_init_tpl();
28 if (ret) {
29 debug("%s: x86_cpu_init_tpl() failed\n", __func__);
30 return ret;
31 }
32 ret = spl_init();
33 if (ret) {
34 debug("%s: spl_init() failed\n", __func__);
35 return ret;
36 }
37 ret = arch_cpu_init();
38 if (ret) {
39 debug("%s: arch_cpu_init() failed\n", __func__);
40 return ret;
41 }
42 ret = arch_cpu_init_dm();
43 if (ret) {
44 debug("%s: arch_cpu_init_dm() failed\n", __func__);
45 return ret;
46 }
47 preloader_console_init();
48
49 return 0;
50 }
51
board_init_f(ulong flags)52 void board_init_f(ulong flags)
53 {
54 int ret;
55
56 ret = x86_tpl_init();
57 if (ret) {
58 debug("Error %d\n", ret);
59 panic("x86_tpl_init fail");
60 }
61
62 /* Uninit CAR and jump to board_init_f_r() */
63 board_init_r(gd, 0);
64 }
65
board_init_f_r(void)66 void board_init_f_r(void)
67 {
68 /* Not used since we never call board_init_f_r_trampoline() */
69 while (1);
70 }
71
spl_boot_device(void)72 u32 spl_boot_device(void)
73 {
74 return IS_ENABLED(CONFIG_CHROMEOS) ? BOOT_DEVICE_CROS_VBOOT :
75 BOOT_DEVICE_SPI_MMAP;
76 }
77
spl_start_uboot(void)78 int spl_start_uboot(void)
79 {
80 return 0;
81 }
82
spl_board_announce_boot_device(void)83 void spl_board_announce_boot_device(void)
84 {
85 printf("SPI flash");
86 }
87
spl_board_load_image(struct spl_image_info * spl_image,struct spl_boot_device * bootdev)88 static int spl_board_load_image(struct spl_image_info *spl_image,
89 struct spl_boot_device *bootdev)
90 {
91 spl_image->size = CONFIG_SYS_MONITOR_LEN; /* We don't know SPL size */
92 spl_image->entry_point = CONFIG_SPL_TEXT_BASE;
93 spl_image->load_addr = CONFIG_SPL_TEXT_BASE;
94 spl_image->os = IH_OS_U_BOOT;
95 spl_image->name = "U-Boot";
96
97 debug("Loading to %lx\n", spl_image->load_addr);
98
99 return 0;
100 }
101 SPL_LOAD_IMAGE_METHOD("SPI", 5, BOOT_DEVICE_SPI_MMAP, spl_board_load_image);
102
spl_spi_load_image(void)103 int spl_spi_load_image(void)
104 {
105 return -EPERM;
106 }
107
jump_to_image_no_args(struct spl_image_info * spl_image)108 void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
109 {
110 debug("Jumping to U-Boot SPL at %lx\n", (ulong)spl_image->entry_point);
111 jump_to_spl(spl_image->entry_point);
112 hang();
113 }
114
spl_board_init(void)115 void spl_board_init(void)
116 {
117 preloader_console_init();
118 }
119
120 #if !CONFIG_IS_ENABLED(PCI)
121 /*
122 * This is a fake PCI bus for TPL when it doesn't have proper PCI. It is enough
123 * to bind the devices on the PCI bus, some of which have early-regs properties
124 * providing fixed BARs. Individual drivers program these BARs themselves so
125 * that they can access the devices. The BARs are allocated statically in the
126 * device tree.
127 *
128 * Once SPL is running it enables PCI properly, but does not auto-assign BARs
129 * for devices, so the TPL BARs continue to be used. Once U-Boot starts it does
130 * the auto allocation (after relocation).
131 */
132 static const struct udevice_id tpl_fake_pci_ids[] = {
133 { .compatible = "pci-x86" },
134 { }
135 };
136
137 U_BOOT_DRIVER(pci_x86) = {
138 .name = "pci_x86",
139 .id = UCLASS_SIMPLE_BUS,
140 .of_match = tpl_fake_pci_ids,
141 };
142 #endif
143