1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Board functions for BuR BRPPT2 board
4 *
5 * Copyright (C) 2019
6 * B&R Industrial Automation GmbH - http://www.br-automation.com/
7 *
8 */
9 #include <common.h>
10 #include <spl.h>
11 #include <dm.h>
12 #include <miiphy.h>
13 #include <asm/arch/crm_regs.h>
14 #include <asm/arch/sys_proto.h>
15 #include <asm/arch/iomux.h>
16 #include <asm/arch/mx6-pins.h>
17 #ifdef CONFIG_SPL_BUILD
18 # include <asm/arch/mx6-ddr.h>
19 #endif
20 #include <asm/arch/clock.h>
21 #include <asm/io.h>
22 #include <asm/gpio.h>
23
24 #define USBHUB_RSTN IMX_GPIO_NR(1, 16)
25 #define BKLT_EN IMX_GPIO_NR(1, 15)
26 #define CAPT_INT IMX_GPIO_NR(4, 9)
27 #define CAPT_RESETN IMX_GPIO_NR(4, 11)
28 #define SW_INTN IMX_GPIO_NR(3, 26)
29 #define VCCDISP_EN IMX_GPIO_NR(5, 18)
30 #define EMMC_RSTN IMX_GPIO_NR(6, 8)
31 #define PMIC_IRQN IMX_GPIO_NR(5, 22)
32 #define TASTER IMX_GPIO_NR(5, 23)
33
34 #define ETH0_LINK IMX_GPIO_NR(1, 27)
35 #define ETH1_LINK IMX_GPIO_NR(1, 28)
36
37 #define UART_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
38 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm | \
39 PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
40
41 #define I2C_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
42 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm | \
43 PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
44
45 #define ECSPI_PAD_CTRL (PAD_CTL_PUS_100K_DOWN | \
46 PAD_CTL_SPEED_MED | PAD_CTL_DSE_48ohm | \
47 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
48 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
49 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm | \
50 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
51
52 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
53 PAD_CTL_SPEED_MED | PAD_CTL_DSE_60ohm | \
54 PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
55
56 #define ENET_PAD_CTRL1 (PAD_CTL_PUS_100K_UP | \
57 PAD_CTL_SPEED_MED | PAD_CTL_DSE_34ohm | \
58 PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
59
60 #define ENET_PAD_CTRL_PU (PAD_CTL_PUS_100K_UP | \
61 PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm | \
62 PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
63
64 #define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
65 PAD_CTL_SPEED_MED | PAD_CTL_DSE_60ohm | \
66 PAD_CTL_SRE_FAST)
67
68 #define GPIO_PAD_CTRL_PU (PAD_CTL_PUS_100K_UP | \
69 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm | \
70 PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
71
72 #define GPIO_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \
73 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm | \
74 PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
75
76 #define LCDCMOS_PAD_CTRL (PAD_CTL_PUS_100K_DOWN | \
77 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_120ohm |\
78 PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
79
80 #define MUXDESC(pad, ctrl) IOMUX_PADS(pad | MUX_PAD_CTRL(ctrl))
81
82 #if !defined(CONFIG_SPL_BUILD)
83 static iomux_v3_cfg_t const eth_pads[] = {
84 /*
85 * Gigabit Ethernet
86 */
87 /* CLKs */
88 MUXDESC(PAD_GPIO_16__ENET_REF_CLK, ENET_PAD_CTRL_CLK),
89 MUXDESC(PAD_ENET_REF_CLK__ENET_TX_CLK, ENET_PAD_CTRL_CLK),
90 /* MDIO */
91 MUXDESC(PAD_ENET_MDIO__ENET_MDIO, ENET_PAD_CTRL_PU),
92 MUXDESC(PAD_ENET_MDC__ENET_MDC, ENET_PAD_CTRL_PU),
93 /* RGMII */
94 MUXDESC(PAD_RGMII_TXC__RGMII_TXC, ENET_PAD_CTRL1),
95 MUXDESC(PAD_RGMII_TD0__RGMII_TD0, ENET_PAD_CTRL),
96 MUXDESC(PAD_RGMII_TD1__RGMII_TD1, ENET_PAD_CTRL),
97 MUXDESC(PAD_RGMII_TD2__RGMII_TD2, ENET_PAD_CTRL),
98 MUXDESC(PAD_RGMII_TD3__RGMII_TD3, ENET_PAD_CTRL),
99 MUXDESC(PAD_RGMII_TX_CTL__RGMII_TX_CTL, ENET_PAD_CTRL),
100 MUXDESC(PAD_RGMII_RXC__RGMII_RXC, ENET_PAD_CTRL_PU),
101 MUXDESC(PAD_RGMII_RD0__RGMII_RD0, ENET_PAD_CTRL_PU),
102 MUXDESC(PAD_RGMII_RD1__RGMII_RD1, ENET_PAD_CTRL_PU),
103 MUXDESC(PAD_RGMII_RD2__RGMII_RD2, ENET_PAD_CTRL_PU),
104 MUXDESC(PAD_RGMII_RD3__RGMII_RD3, ENET_PAD_CTRL_PU),
105 MUXDESC(PAD_RGMII_RX_CTL__RGMII_RX_CTL, ENET_PAD_CTRL_PU),
106 /* ETH0_LINK */
107 MUXDESC(PAD_ENET_RXD0__GPIO1_IO27, GPIO_PAD_CTRL_PD),
108 /* ETH1_LINK */
109 MUXDESC(PAD_ENET_TX_EN__GPIO1_IO28, GPIO_PAD_CTRL_PD),
110 };
111
112 static iomux_v3_cfg_t const board_pads[] = {
113 /*
114 * I2C #3, #4
115 */
116 MUXDESC(PAD_GPIO_3__I2C3_SCL, I2C_PAD_CTRL),
117 MUXDESC(PAD_GPIO_6__I2C3_SDA, I2C_PAD_CTRL),
118
119 /*
120 * UART#4 PADS
121 * UART_Tasten
122 */
123 MUXDESC(PAD_CSI0_DAT12__UART4_TX_DATA, UART_PAD_CTRL),
124 MUXDESC(PAD_CSI0_DAT13__UART4_RX_DATA, UART_PAD_CTRL),
125 MUXDESC(PAD_CSI0_DAT17__UART4_CTS_B, UART_PAD_CTRL),
126 MUXDESC(PAD_CSI0_DAT16__UART4_RTS_B, UART_PAD_CTRL),
127 /*
128 * ESCPI#1
129 * M25P32 NOR-Flash
130 */
131 MUXDESC(PAD_EIM_D16__ECSPI1_SCLK, ECSPI_PAD_CTRL),
132 MUXDESC(PAD_EIM_D17__ECSPI1_MISO, ECSPI_PAD_CTRL),
133 MUXDESC(PAD_EIM_D18__ECSPI1_MOSI, ECSPI_PAD_CTRL),
134 MUXDESC(PAD_EIM_D19__GPIO3_IO19, ECSPI_PAD_CTRL),
135 /*
136 * ESCPI#2
137 * resTouch SPI ADC
138 */
139 MUXDESC(PAD_CSI0_DAT8__ECSPI2_SCLK, ECSPI_PAD_CTRL),
140 MUXDESC(PAD_EIM_OE__ECSPI2_MISO, ECSPI_PAD_CTRL),
141 MUXDESC(PAD_CSI0_DAT9__ECSPI2_MOSI, ECSPI_PAD_CTRL),
142 MUXDESC(PAD_EIM_D24__GPIO3_IO24, ECSPI_PAD_CTRL),
143 /*
144 * USDHC#4
145 */
146 MUXDESC(PAD_SD4_CLK__SD4_CLK, USDHC_PAD_CTRL),
147 MUXDESC(PAD_SD4_CMD__SD4_CMD, USDHC_PAD_CTRL),
148 MUXDESC(PAD_SD4_DAT0__SD4_DATA0, USDHC_PAD_CTRL),
149 MUXDESC(PAD_SD4_DAT1__SD4_DATA1, USDHC_PAD_CTRL),
150 MUXDESC(PAD_SD4_DAT2__SD4_DATA2, USDHC_PAD_CTRL),
151 MUXDESC(PAD_SD4_DAT3__SD4_DATA3, USDHC_PAD_CTRL),
152 MUXDESC(PAD_SD4_DAT4__SD4_DATA4, USDHC_PAD_CTRL),
153 MUXDESC(PAD_SD4_DAT5__SD4_DATA5, USDHC_PAD_CTRL),
154 MUXDESC(PAD_SD4_DAT6__SD4_DATA6, USDHC_PAD_CTRL),
155 MUXDESC(PAD_SD4_DAT7__SD4_DATA7, USDHC_PAD_CTRL),
156 /*
157 * USB OTG power & ID
158 */
159 /* USB_OTG_5V_EN */
160 MUXDESC(PAD_EIM_D22__GPIO3_IO22, GPIO_PAD_CTRL_PD),
161 MUXDESC(PAD_EIM_D31__GPIO3_IO31, GPIO_PAD_CTRL_PD),
162 /* USB_OTG_JUMPER */
163 MUXDESC(PAD_ENET_RX_ER__USB_OTG_ID, GPIO_PAD_CTRL_PD),
164 /*
165 * PWM-Pins
166 */
167 /* BKLT_CTL */
168 MUXDESC(PAD_SD1_CMD__PWM4_OUT, GPIO_PAD_CTRL_PD),
169 /* SPEAKER */
170 MUXDESC(PAD_SD1_DAT1__PWM3_OUT, GPIO_PAD_CTRL_PD),
171 /*
172 * GPIOs
173 */
174 /* USB_HUB_nRESET */
175 MUXDESC(PAD_SD1_DAT0__GPIO1_IO16, GPIO_PAD_CTRL_PD),
176 /* BKLT_EN */
177 MUXDESC(PAD_SD2_DAT0__GPIO1_IO15, GPIO_PAD_CTRL_PD),
178 /* capTouch_INT */
179 MUXDESC(PAD_KEY_ROW1__GPIO4_IO09, GPIO_PAD_CTRL_PD),
180 /* capTouch_nRESET */
181 MUXDESC(PAD_KEY_ROW2__GPIO4_IO11, GPIO_PAD_CTRL_PD),
182 /* SW_nINT */
183 MUXDESC(PAD_EIM_D26__GPIO3_IO26, GPIO_PAD_CTRL_PU),
184 /* VCC_DISP_EN */
185 MUXDESC(PAD_CSI0_PIXCLK__GPIO5_IO18, GPIO_PAD_CTRL_PD),
186 /* eMMC_nRESET */
187 MUXDESC(PAD_NANDF_ALE__GPIO6_IO08, GPIO_PAD_CTRL_PD),
188 /* HWID*/
189 MUXDESC(PAD_NANDF_D0__GPIO2_IO00, GPIO_PAD_CTRL_PU),
190 MUXDESC(PAD_NANDF_D1__GPIO2_IO01, GPIO_PAD_CTRL_PU),
191 MUXDESC(PAD_NANDF_D2__GPIO2_IO02, GPIO_PAD_CTRL_PU),
192 MUXDESC(PAD_NANDF_D3__GPIO2_IO03, GPIO_PAD_CTRL_PU),
193 /* PMIC_nIRQ */
194 MUXDESC(PAD_CSI0_DAT4__GPIO5_IO22, GPIO_PAD_CTRL_PU),
195 /* nTASTER */
196 MUXDESC(PAD_CSI0_DAT5__GPIO5_IO23, GPIO_PAD_CTRL_PU),
197 /* RGB LCD Display */
198 MUXDESC(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, LCDCMOS_PAD_CTRL),
199 MUXDESC(PAD_DI0_PIN2__IPU1_DI0_PIN02, LCDCMOS_PAD_CTRL),
200 MUXDESC(PAD_DI0_PIN3__IPU1_DI0_PIN03, LCDCMOS_PAD_CTRL),
201 MUXDESC(PAD_DI0_PIN4__IPU1_DI0_PIN04, LCDCMOS_PAD_CTRL),
202 MUXDESC(PAD_DI0_PIN15__IPU1_DI0_PIN15, LCDCMOS_PAD_CTRL),
203 MUXDESC(PAD_DISP0_DAT0__IPU1_DISP0_DATA00, LCDCMOS_PAD_CTRL),
204 MUXDESC(PAD_DISP0_DAT1__IPU1_DISP0_DATA01, LCDCMOS_PAD_CTRL),
205 MUXDESC(PAD_DISP0_DAT2__IPU1_DISP0_DATA02, LCDCMOS_PAD_CTRL),
206 MUXDESC(PAD_DISP0_DAT3__IPU1_DISP0_DATA03, LCDCMOS_PAD_CTRL),
207 MUXDESC(PAD_DISP0_DAT4__IPU1_DISP0_DATA04, LCDCMOS_PAD_CTRL),
208 MUXDESC(PAD_DISP0_DAT5__IPU1_DISP0_DATA05, LCDCMOS_PAD_CTRL),
209 MUXDESC(PAD_DISP0_DAT6__IPU1_DISP0_DATA06, LCDCMOS_PAD_CTRL),
210 MUXDESC(PAD_DISP0_DAT7__IPU1_DISP0_DATA07, LCDCMOS_PAD_CTRL),
211 MUXDESC(PAD_DISP0_DAT8__IPU1_DISP0_DATA08, LCDCMOS_PAD_CTRL),
212 MUXDESC(PAD_DISP0_DAT9__IPU1_DISP0_DATA09, LCDCMOS_PAD_CTRL),
213 MUXDESC(PAD_DISP0_DAT10__IPU1_DISP0_DATA10, LCDCMOS_PAD_CTRL),
214 MUXDESC(PAD_DISP0_DAT11__IPU1_DISP0_DATA11, LCDCMOS_PAD_CTRL),
215 MUXDESC(PAD_DISP0_DAT12__IPU1_DISP0_DATA12, LCDCMOS_PAD_CTRL),
216 MUXDESC(PAD_DISP0_DAT13__IPU1_DISP0_DATA13, LCDCMOS_PAD_CTRL),
217 MUXDESC(PAD_DISP0_DAT14__IPU1_DISP0_DATA14, LCDCMOS_PAD_CTRL),
218 MUXDESC(PAD_DISP0_DAT15__IPU1_DISP0_DATA15, LCDCMOS_PAD_CTRL),
219 MUXDESC(PAD_DISP0_DAT16__IPU1_DISP0_DATA16, LCDCMOS_PAD_CTRL),
220 MUXDESC(PAD_DISP0_DAT17__IPU1_DISP0_DATA17, LCDCMOS_PAD_CTRL),
221 MUXDESC(PAD_DISP0_DAT18__IPU1_DISP0_DATA18, LCDCMOS_PAD_CTRL),
222 MUXDESC(PAD_DISP0_DAT19__IPU1_DISP0_DATA19, LCDCMOS_PAD_CTRL),
223 MUXDESC(PAD_DISP0_DAT20__IPU1_DISP0_DATA20, LCDCMOS_PAD_CTRL),
224 MUXDESC(PAD_DISP0_DAT21__IPU1_DISP0_DATA21, LCDCMOS_PAD_CTRL),
225 MUXDESC(PAD_DISP0_DAT22__IPU1_DISP0_DATA22, LCDCMOS_PAD_CTRL),
226 MUXDESC(PAD_DISP0_DAT23__IPU1_DISP0_DATA23, LCDCMOS_PAD_CTRL),
227 };
228
board_ehci_hcd_init(int port)229 int board_ehci_hcd_init(int port)
230 {
231 gpio_direction_output(USBHUB_RSTN, 1);
232
233 return 0;
234 }
235
board_late_init(void)236 int board_late_init(void)
237 {
238 ulong b_mode = 4;
239
240 if (gpio_get_value(TASTER) == 0)
241 b_mode = 12;
242
243 env_set_ulong("b_mode", b_mode);
244
245 return 0;
246 }
247
board_init(void)248 int board_init(void)
249 {
250 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
251
252 if (gpio_request(BKLT_EN, "BKLT_EN"))
253 printf("Warning: BKLT_EN setup failed\n");
254 gpio_direction_output(BKLT_EN, 0);
255
256 if (gpio_request(USBHUB_RSTN, "USBHUB_nRST"))
257 printf("Warning: USBHUB_nRST setup failed\n");
258 gpio_direction_output(USBHUB_RSTN, 0);
259
260 if (gpio_request(TASTER, "TASTER"))
261 printf("Warning: TASTER setup failed\n");
262 gpio_direction_input(TASTER);
263
264 return 0;
265 }
266
board_early_init_f(void)267 int board_early_init_f(void)
268 {
269 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
270
271 SETUP_IOMUX_PADS(board_pads);
272 SETUP_IOMUX_PADS(eth_pads);
273
274 /* set GPIO_16 as ENET_REF_CLK_OUT running at 25 MHz */
275 setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
276 enable_fec_anatop_clock(0, ENET_25MHZ);
277 enable_enet_clk(1);
278
279 return 0;
280 }
281
dram_init(void)282 int dram_init(void)
283 {
284 gd->ram_size = imx_ddr_size();
285
286 return 0;
287 }
288 #else
289 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
290 static struct mx6sdl_iomux_ddr_regs ddr_iomux_s = {
291 /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
292 .dram_sdclk_0 = 0x00020030,
293 .dram_sdclk_1 = 0x00020030,
294 .dram_cas = 0x00020030,
295 .dram_ras = 0x00020030,
296 .dram_reset = 0x00020030,
297 /* SDCKE[0:1]: 100k pull-up */
298 .dram_sdcke0 = 0x00003000,
299 .dram_sdcke1 = 0x00003000,
300 /* SDBA2: pull-up disabled */
301 .dram_sdba2 = 0x00000000,
302 /* SDODT[0:1]: 100k pull-up, 40 ohm */
303 .dram_sdodt0 = 0x00003030,
304 .dram_sdodt1 = 0x00003030,
305 /* SDQS[0:7]: Differential input, 40 ohm */
306 .dram_sdqs0 = 0x00000030,
307 .dram_sdqs1 = 0x00000030,
308 .dram_sdqs2 = 0x00000030,
309 .dram_sdqs3 = 0x00000030,
310 .dram_sdqs4 = 0x00000030,
311 .dram_sdqs5 = 0x00000030,
312 .dram_sdqs6 = 0x00000030,
313 .dram_sdqs7 = 0x00000030,
314 /* DQM[0:7]: Differential input, 40 ohm */
315 .dram_dqm0 = 0x00020030,
316 .dram_dqm1 = 0x00020030,
317 .dram_dqm2 = 0x00020030,
318 .dram_dqm3 = 0x00020030,
319 .dram_dqm4 = 0x00020030,
320 .dram_dqm5 = 0x00020030,
321 .dram_dqm6 = 0x00020030,
322 .dram_dqm7 = 0x00020030,
323 };
324
325 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
326 static struct mx6sdl_iomux_grp_regs grp_iomux_s = {
327 /* DDR3 */
328 .grp_ddr_type = 0x000c0000,
329 .grp_ddrmode_ctl = 0x00020000,
330 /* disable DDR pullups */
331 .grp_ddrpke = 0x00000000,
332 /* ADDR[00:16], SDBA[0:1]: 40 ohm */
333 .grp_addds = 0x00000030,
334 /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
335 .grp_ctlds = 0x00000030,
336 /* DATA[00:63]: Differential input, 40 ohm */
337 .grp_ddrmode = 0x00020000,
338 .grp_b0ds = 0x00000030,
339 .grp_b1ds = 0x00000030,
340 .grp_b2ds = 0x00000030,
341 .grp_b3ds = 0x00000030,
342 .grp_b4ds = 0x00000030,
343 .grp_b5ds = 0x00000030,
344 .grp_b6ds = 0x00000030,
345 .grp_b7ds = 0x00000030,
346 };
347
348 /*
349 * DDR3 desriptions - these are the memory chips we support
350 */
351
352 /* NT5CC128M16FP-DII */
353 static struct mx6_ddr3_cfg cfg_nt5cc128m16fp_dii = {
354 .mem_speed = 1600,
355 .density = 2,
356 .width = 16,
357 .banks = 8,
358 .rowaddr = 14,
359 .coladdr = 10,
360 .pagesz = 2,
361 .trcd = 1375,
362 .trcmin = 4875,
363 .trasmin = 3500,
364 };
365
366 /* measured on board TSERIES_ARM/1 V_LVDS_DL64 */
367 static struct mx6_mmdc_calibration cal_nt5cc128m16fp_dii_128x64_s = {
368 /* write leveling calibration determine, MR1-value = 0x0002 */
369 .p0_mpwldectrl0 = 0x003F003E,
370 .p0_mpwldectrl1 = 0x003A003A,
371 .p1_mpwldectrl0 = 0x001B001C,
372 .p1_mpwldectrl1 = 0x00190031,
373 /* Read DQS Gating calibration */
374 .p0_mpdgctrl0 = 0x02640264,
375 .p0_mpdgctrl1 = 0x02440250,
376 .p1_mpdgctrl0 = 0x02400250,
377 .p1_mpdgctrl1 = 0x0238023C,
378 /* Read Calibration: DQS delay relative to DQ read access */
379 .p0_mprddlctl = 0x40464644,
380 .p1_mprddlctl = 0x464A4842,
381 /* Write Calibration: DQ/DM delay relative to DQS write access */
382 .p0_mpwrdlctl = 0x38343034,
383 .p1_mpwrdlctl = 0x36323830,
384 };
385
386 /* measured on board TSERIES_ARM/1 V_LVDS_S32 */
387 static struct mx6_mmdc_calibration cal_nt5cc128m16fp_dii_128x32_s = {
388 /* write leveling calibration determine, MR1-value = 0x0002 */
389 .p0_mpwldectrl0 = 0x00410043,
390 .p0_mpwldectrl1 = 0x003A003C,
391 /* Read DQS Gating calibration */
392 .p0_mpdgctrl0 = 0x023C0244,
393 .p0_mpdgctrl1 = 0x02240230,
394 /* Read Calibration: DQS delay relative to DQ read access */
395 .p0_mprddlctl = 0x484C4A48,
396 /* Write Calibration: DQ/DM delay relative to DQS write access */
397 .p0_mpwrdlctl = 0x3C363434,
398 };
399
spl_dram_init(void)400 static void spl_dram_init(void)
401 {
402 struct gpio_regs *gpio = (struct gpio_regs *)GPIO2_BASE_ADDR;
403 u32 val, dram_strap = 0;
404 struct mx6_ddr3_cfg *mem = NULL;
405 struct mx6_mmdc_calibration *calib = NULL;
406 struct mx6_ddr_sysinfo sysinfo = {
407 /* width of data bus:0=16,1=32,2=64 */
408 .dsize = -1, /* CPU type specific (overwritten) */
409 /* config for full 4GB range so that get_mem_size() works */
410 .cs_density = 32, /* 32Gb per CS */
411 .ncs = 1, /* single chip select */
412 .cs1_mirror = 0,
413 .rtt_wr = 1, /* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */
414 .rtt_nom = 1, /* DDR3_RTT_60_OHM, RTT_Nom = RZQ/4 */
415 .walat = 1, /* Write additional latency */
416 .ralat = 5, /* Read additional latency */
417 .mif3_mode = 3, /* Command prediction working mode */
418 .bi_on = 1, /* Bank interleaving enabled */
419 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
420 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
421 .ddr_type = 0, /* DDR3 */
422 };
423
424 /*
425 * MMDC Calibration requires the following data:
426 * mx6_mmdc_calibration - board-specific calibration (routing delays)
427 * these calibration values depend on board routing, SoC, and DDR
428 * mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc)
429 * mx6_ddr_cfg - chip specific timing/layout details
430 */
431
432 /* setup HWID3-2 to input */
433 val = readl(&gpio->gpio_dir);
434 val &= ~(0x1 << 0 | 0x1 << 1);
435 writel(val, &gpio->gpio_dir);
436
437 /* read DRAM strapping from HWID3/2 (bit 1 and bit 0) */
438 dram_strap = readl(&gpio->gpio_psr) & 0x3;
439
440 switch (dram_strap) {
441 /* 1 GiB, 64 bit, 4 NT5CC128M16FP chips */
442 case 0:
443 puts("DRAM strap 00\n");
444 mem = &cfg_nt5cc128m16fp_dii;
445 sysinfo.dsize = 2;
446 calib = &cal_nt5cc128m16fp_dii_128x64_s;
447 break;
448 /* 512 MiB, 32 bit, 2 NT5CC128M16FP chips */
449 case 1:
450 puts("DRAM strap 01\n");
451 mem = &cfg_nt5cc128m16fp_dii;
452 sysinfo.dsize = 1;
453 calib = &cal_nt5cc128m16fp_dii_128x32_s;
454 break;
455 default:
456 printf("DRAM strap 0x%x (invalid)\n", dram_strap);
457 break;
458 }
459
460 if (!mem) {
461 puts("Error: Invalid Memory Configuration\n");
462 hang();
463 }
464 if (!calib) {
465 puts("Error: Invalid Board Calibration Configuration\n");
466 hang();
467 }
468
469 mx6sdl_dram_iocfg(16 << sysinfo.dsize,
470 &ddr_iomux_s,
471 &grp_iomux_s);
472
473 mx6_dram_cfg(&sysinfo, calib, mem);
474 }
475
476 static iomux_v3_cfg_t const board_pads_spl[] = {
477 /* UART#1 PADS */
478 MUXDESC(PAD_CSI0_DAT10__UART1_TX_DATA, UART_PAD_CTRL),
479 MUXDESC(PAD_CSI0_DAT11__UART1_RX_DATA, UART_PAD_CTRL),
480 /* ESCPI#1 PADS */
481 MUXDESC(PAD_EIM_D16__ECSPI1_SCLK, ECSPI_PAD_CTRL),
482 MUXDESC(PAD_EIM_D17__ECSPI1_MISO, ECSPI_PAD_CTRL),
483 MUXDESC(PAD_EIM_D18__ECSPI1_MOSI, ECSPI_PAD_CTRL),
484 MUXDESC(PAD_EIM_D19__GPIO3_IO19, ECSPI_PAD_CTRL),
485 /* USDHC#4 PADS */
486 MUXDESC(PAD_SD4_CLK__SD4_CLK, USDHC_PAD_CTRL),
487 MUXDESC(PAD_SD4_CMD__SD4_CMD, USDHC_PAD_CTRL),
488 MUXDESC(PAD_SD4_DAT0__SD4_DATA0, USDHC_PAD_CTRL),
489 MUXDESC(PAD_SD4_DAT1__SD4_DATA1, USDHC_PAD_CTRL),
490 MUXDESC(PAD_SD4_DAT2__SD4_DATA2, USDHC_PAD_CTRL),
491 MUXDESC(PAD_SD4_DAT3__SD4_DATA3, USDHC_PAD_CTRL),
492 MUXDESC(PAD_SD4_DAT4__SD4_DATA4, USDHC_PAD_CTRL),
493 MUXDESC(PAD_SD4_DAT5__SD4_DATA5, USDHC_PAD_CTRL),
494 MUXDESC(PAD_SD4_DAT6__SD4_DATA6, USDHC_PAD_CTRL),
495 MUXDESC(PAD_SD4_DAT7__SD4_DATA7, USDHC_PAD_CTRL),
496 /* HWID*/
497 MUXDESC(PAD_NANDF_D0__GPIO2_IO00, GPIO_PAD_CTRL_PU),
498 MUXDESC(PAD_NANDF_D1__GPIO2_IO01, GPIO_PAD_CTRL_PU),
499 MUXDESC(PAD_NANDF_D2__GPIO2_IO02, GPIO_PAD_CTRL_PU),
500 MUXDESC(PAD_NANDF_D3__GPIO2_IO03, GPIO_PAD_CTRL_PU),
501 };
502
spl_board_init(void)503 void spl_board_init(void)
504 {
505 preloader_console_init();
506 }
507
ccgr_init(void)508 static void ccgr_init(void)
509 {
510 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
511
512 /*
513 * We don't use DMA in SPL, but we do need it in U-Boot. U-Boot
514 * initializes DMA very early (before all board code), so the only
515 * opportunity we have to initialize APBHDMA clocks is in SPL.
516 * setbits_le32(&ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
517 */
518
519 writel(0x00C03F3F, &ccm->CCGR0);
520 writel(0x00F0FC03, &ccm->CCGR1);
521 writel(0x0FFFF000, &ccm->CCGR2);
522 writel(0x3FF00000, &ccm->CCGR3);
523 writel(0x00FFF300, &ccm->CCGR4);
524 writel(0x0F0030C3, &ccm->CCGR5);
525 writel(0x000003F0, &ccm->CCGR6);
526 }
527
board_init_f(ulong dummy)528 void board_init_f(ulong dummy)
529 {
530 ccgr_init();
531 arch_cpu_init();
532 timer_init();
533 gpr_init();
534
535 SETUP_IOMUX_PADS(board_pads_spl);
536 spl_dram_init();
537 }
538
reset_cpu(ulong addr)539 void reset_cpu(ulong addr)
540 {
541 }
542 #endif /* CONFIG_SPL_BUILD */
543