1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * board.c
4 *
5 * Board functions for B&R BRXRE1 Board
6 *
7 * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
8 * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
9 *
10 */
11 #include <common.h>
12 #include <env.h>
13 #include <errno.h>
14 #include <init.h>
15 #include <spl.h>
16 #include <asm/arch/cpu.h>
17 #include <asm/arch/hardware.h>
18 #include <asm/arch/omap.h>
19 #include <asm/arch/ddr_defs.h>
20 #include <asm/arch/clock.h>
21 #include <asm/arch/gpio.h>
22 #include <asm/arch/sys_proto.h>
23 #include <asm/arch/mem.h>
24 #include <asm/io.h>
25 #include <asm/emif.h>
26 #include <asm/gpio.h>
27 #include <dm.h>
28 #include <power/tps65217.h>
29 #include "../common/bur_common.h"
30 #include "../common/br_resetc.h"
31
32 /* -------------------------------------------------------------------------*/
33 /* -- defines for used GPIO Hardware -- */
34 #define ESC_KEY (0 + 19)
35 #define LCD_PWR (0 + 5)
36
37 #define RSTCTRL_FORCE_PWR_NEN 0x04
38 #define RSTCTRL_CAN_STB 0x40
39
40 DECLARE_GLOBAL_DATA_PTR;
41
42 #if defined(CONFIG_SPL_BUILD)
43 static const struct ddr_data ddr3_data = {
44 .datardsratio0 = MT41K256M16HA125E_RD_DQS,
45 .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
46 .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
47 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
48 };
49
50 static const struct cmd_control ddr3_cmd_ctrl_data = {
51 .cmd0csratio = MT41K256M16HA125E_RATIO,
52 .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
53
54 .cmd1csratio = MT41K256M16HA125E_RATIO,
55 .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
56
57 .cmd2csratio = MT41K256M16HA125E_RATIO,
58 .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
59 };
60
61 static struct emif_regs ddr3_emif_reg_data = {
62 .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
63 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
64 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
65 .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
66 .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
67 .zq_config = MT41K256M16HA125E_ZQ_CFG,
68 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
69 };
70
71 static const struct ctrl_ioregs ddr3_ioregs = {
72 .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
73 .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
74 .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
75 .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
76 .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
77 };
78
79 #define OSC (V_OSCK / 1000000)
80 const struct dpll_params dpll_ddr3 = { 400, OSC - 1, 1, -1, -1, -1, -1};
81
am33xx_spl_board_init(void)82 void am33xx_spl_board_init(void)
83 {
84 int rc;
85
86 struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
87 struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
88 /*
89 * enable additional clocks of modules which are accessed later from
90 * VxWorks OS
91 */
92 u32 *const clk_domains[] = { 0 };
93
94 u32 *const clk_modules_xre1specific[] = {
95 &cmwkup->wkup_adctscctrl,
96 &cmper->spi1clkctrl,
97 &cmper->dcan0clkctrl,
98 &cmper->dcan1clkctrl,
99 &cmper->epwmss0clkctrl,
100 &cmper->epwmss1clkctrl,
101 &cmper->epwmss2clkctrl,
102 &cmper->lcdclkctrl,
103 &cmper->lcdcclkstctrl,
104 0
105 };
106 do_enable_clocks(clk_domains, clk_modules_xre1specific, 1);
107 /* power-OFF LCD-Display */
108 if (gpio_request(LCD_PWR, "LCD_PWR") != 0)
109 printf("cannot request gpio for LCD_PWR!\n");
110 else if (gpio_direction_output(LCD_PWR, 0) != 0)
111 printf("cannot set direction output on LCD_PWR!\n");
112
113 /* setup I2C */
114 enable_i2c_pin_mux();
115
116 /* power-ON 3V3 via Resetcontroller */
117 rc = br_resetc_regset(RSTCTRL_CTRLREG,
118 RSTCTRL_FORCE_PWR_NEN | RSTCTRL_CAN_STB);
119 if (rc != 0)
120 printf("ERROR: cannot write to resetc (turn on PWR_nEN)!\n");
121
122 pmicsetup(0, 0);
123 }
124
get_dpll_ddr_params(void)125 const struct dpll_params *get_dpll_ddr_params(void)
126 {
127 return &dpll_ddr3;
128 }
129
sdram_init(void)130 void sdram_init(void)
131 {
132 config_ddr(400, &ddr3_ioregs,
133 &ddr3_data,
134 &ddr3_cmd_ctrl_data,
135 &ddr3_emif_reg_data, 0);
136 }
137 #endif /* CONFIG_SPL_BUILD */
138 /*
139 * Basic board specific setup. Pinmux has been handled already.
140 */
board_init(void)141 int board_init(void)
142 {
143 /* request common used gpios */
144 gpio_request(ESC_KEY, "boot-key");
145
146 if (power_tps65217_init(0))
147 printf("WARN: cannot setup PMIC 0x24 @ bus #0, not found!.\n");
148
149 return 0;
150 }
151
152 #ifdef CONFIG_BOARD_LATE_INIT
153
board_boot_key(void)154 int board_boot_key(void)
155 {
156 return gpio_get_value(ESC_KEY);
157 }
158
board_late_init(void)159 int board_late_init(void)
160 {
161 char othbootargs[128];
162
163 br_resetc_bmode();
164
165 /* setup othbootargs for bootvx-command (vxWorks bootline) */
166 snprintf(othbootargs, sizeof(othbootargs),
167 "u=vxWorksFTP pw=vxWorks o=0x%08x;0x%08x;0x%08x;0x%08x",
168 (u32)gd->fb_base - 0x20,
169 (u32)env_get_ulong("vx_memtop", 16, gd->fb_base - 0x20),
170 (u32)env_get_ulong("vx_romfsbase", 16, 0),
171 (u32)env_get_ulong("vx_romfssize", 16, 0));
172 env_set("othbootargs", othbootargs);
173 /*
174 * reset VBAR registers to its reset location, VxWorks 6.9.3.2 does
175 * expect that vectors are there, original u-boot moves them to _start
176 */
177 __asm__("ldr r0,=0x20000");
178 __asm__("mcr p15, 0, r0, c12, c0, 0"); /* Set VBAR */
179
180 return 0;
181 }
182 #endif /* CONFIG_BOARD_LATE_INIT */
183