1 // SPDX-License-Identifier: GPL-2.0+
2
3 #include <common.h>
4 #include <linux/io.h>
5 #include <miiphy.h>
6 #include <netdev.h>
7 #include <asm/arch/cpu.h>
8 #include <asm/arch/soc.h>
9 #include <asm/arch/mpp.h>
10 #include <asm/arch/gpio.h>
11
12 #define DB_88F6281_OE_LOW ~(BIT(7))
13 #define DB_88F6281_OE_HIGH ~(BIT(15) | BIT(14) | BIT(13) | BIT(4))
14 #define DB_88F6281_OE_VAL_LOW BIT(7)
15 #define DB_88F6281_OE_VAL_HIGH 0
16
17 DECLARE_GLOBAL_DATA_PTR;
18
board_early_init_f(void)19 int board_early_init_f(void)
20 {
21 mvebu_config_gpio(DB_88F6281_OE_VAL_LOW,
22 DB_88F6281_OE_VAL_HIGH,
23 DB_88F6281_OE_LOW, DB_88F6281_OE_HIGH);
24
25 /* Multi-Purpose Pins Functionality configuration */
26 static const u32 kwmpp_config[] = {
27 #ifdef CONFIG_CMD_NAND
28 MPP0_NF_IO2,
29 MPP1_NF_IO3,
30 MPP2_NF_IO4,
31 MPP3_NF_IO5,
32 #else
33 MPP0_SPI_SCn,
34 MPP1_SPI_MOSI,
35 MPP2_SPI_SCK,
36 MPP3_SPI_MISO,
37 #endif
38 MPP4_NF_IO6,
39 MPP5_NF_IO7,
40 MPP6_SYSRST_OUTn,
41 MPP7_GPO,
42 MPP8_TW_SDA,
43 MPP9_TW_SCK,
44 MPP10_UART0_TXD,
45 MPP11_UART0_RXD,
46 MPP12_SD_CLK,
47 MPP13_SD_CMD,
48 MPP14_SD_D0,
49 MPP15_SD_D1,
50 MPP16_SD_D2,
51 MPP17_SD_D3,
52 MPP18_NF_IO0,
53 MPP19_NF_IO1,
54 MPP20_SATA1_ACTn,
55 MPP21_SATA0_ACTn,
56 MPP22_GPIO,
57 MPP23_GPIO,
58 MPP24_GPIO,
59 MPP25_GPIO,
60 MPP26_GPIO,
61 MPP27_GPIO,
62 MPP28_GPIO,
63 MPP29_GPIO,
64 MPP30_GPIO,
65 MPP31_GPIO,
66 MPP32_GPIO,
67 MPP33_GPIO,
68 MPP34_GPIO,
69 MPP35_GPIO,
70 MPP36_GPIO,
71 MPP37_GPIO,
72 MPP38_GPIO,
73 MPP39_GPIO,
74 MPP40_GPIO,
75 MPP41_GPIO,
76 MPP42_GPIO,
77 MPP43_GPIO,
78 MPP44_GPIO,
79 MPP45_GPIO,
80 MPP46_GPIO,
81 MPP47_GPIO,
82 MPP48_GPIO,
83 MPP49_GPIO,
84 0
85 };
86 kirkwood_mpp_conf(kwmpp_config, NULL);
87
88 return 0;
89 }
90
board_init(void)91 int board_init(void)
92 {
93 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
94
95 return 0;
96 }
97
98 #ifdef CONFIG_RESET_PHY_R
99 /* automatically defined by kirkwood config.h */
reset_phy(void)100 void reset_phy(void)
101 {
102 }
103 #endif
104