1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2015 Stefan Roese <sr@denx.de>
4 */
5
6 #include <common.h>
7 #include <i2c.h>
8 #include <asm/gpio.h>
9 #include <linux/mbus.h>
10 #include <linux/io.h>
11 #include <asm/arch/cpu.h>
12 #include <asm/arch/soc.h>
13
14 DECLARE_GLOBAL_DATA_PTR;
15
16 /*
17 * These values and defines are taken from the Marvell U-Boot version
18 * "u-boot-2013.01-2016_T1.0.eng_drop_v6"
19 */
20 #define DB_DX_AC3_GPP_OUT_ENA_LOW (~(BIT(0) | BIT(2) | BIT(3) | BIT(4) | BIT(6) | BIT(12) \
21 | BIT(13) | BIT(16) | BIT(17) | BIT(20) | BIT(29) | BIT(30)))
22 #define DB_DX_AC3_GPP_OUT_ENA_MID (~(0))
23 #define DB_DX_AC3_GPP_OUT_VAL_LOW (BIT(0) | BIT(2) | BIT(3) | BIT(4) | BIT(6) | BIT(12) \
24 | BIT(13) | BIT(16) | BIT(17) | BIT(20) | BIT(29) | BIT(30))
25 #define DB_DX_AC3_GPP_OUT_VAL_MID 0x0
26 #define DB_DX_AC3_GPP_POL_LOW 0x0
27 #define DB_DX_AC3_GPP_POL_MID 0x0
28
board_early_init_f(void)29 int board_early_init_f(void)
30 {
31 /* Configure MPP */
32 writel(0x00142222, MVEBU_MPP_BASE + 0x00);
33 writel(0x11122000, MVEBU_MPP_BASE + 0x04);
34 writel(0x44444004, MVEBU_MPP_BASE + 0x08);
35 writel(0x14444444, MVEBU_MPP_BASE + 0x0c);
36 writel(0x00000001, MVEBU_MPP_BASE + 0x10);
37
38 /* Set GPP Out value */
39 writel(DB_DX_AC3_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
40 writel(DB_DX_AC3_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
41
42 /* Set GPP Polarity */
43 writel(DB_DX_AC3_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
44 writel(DB_DX_AC3_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
45
46 /* Set GPP Out Enable */
47 writel(DB_DX_AC3_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
48 writel(DB_DX_AC3_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
49
50 return 0;
51 }
52
board_init(void)53 int board_init(void)
54 {
55 /* address of boot parameters */
56 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
57
58 return 0;
59 }
60
61 #ifdef CONFIG_DISPLAY_BOARDINFO
checkboard(void)62 int checkboard(void)
63 {
64 puts("Board: " CONFIG_SYS_BOARD "\n");
65
66 return 0;
67 }
68 #endif
69