1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2017 Allied Telesis Labs
4 */
5
6 #include <common.h>
7 #include <command.h>
8 #include <dm.h>
9 #include <env.h>
10 #include <i2c.h>
11 #include <wdt.h>
12 #include <asm/gpio.h>
13 #include <linux/mbus.h>
14 #include <linux/io.h>
15 #include <asm/arch/cpu.h>
16 #include <asm/arch/soc.h>
17 #include "../common/gpio_hog.h"
18
19 #include "../drivers/ddr/marvell/a38x/ddr3_init.h"
20 #include <../serdes/a38x/high_speed_env_spec.h>
21
22 DECLARE_GLOBAL_DATA_PTR;
23
24 #define MVEBU_DEV_BUS_BASE (MVEBU_REGISTER(0x10400))
25
26 #define CONFIG_NVS_LOCATION 0xf4800000
27 #define CONFIG_NVS_SIZE (512 << 10)
28
29 static struct serdes_map board_serdes_map[] = {
30 {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
31 {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
32 {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
33 {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
34 {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
35 {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}
36 };
37
hws_board_topology_load(struct serdes_map ** serdes_map_array,u8 * count)38 int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
39 {
40 *serdes_map_array = board_serdes_map;
41 *count = ARRAY_SIZE(board_serdes_map);
42 return 0;
43 }
44
45 /*
46 * Define the DDR layout / topology here in the board file. This will
47 * be used by the DDR3 init code in the SPL U-Boot version to configure
48 * the DDR3 controller.
49 */
50 static struct mv_ddr_topology_map board_topology_map = {
51 DEBUG_LEVEL_ERROR,
52 0x1, /* active interfaces */
53 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
54 { { { {0x1, 0, 0, 0},
55 {0x1, 0, 0, 0},
56 {0x1, 0, 0, 0},
57 {0x1, 0, 0, 0},
58 {0x1, 0, 0, 0} },
59 SPEED_BIN_DDR_1866M, /* speed_bin */
60 MV_DDR_DEV_WIDTH_16BIT, /* sdram device width */
61 MV_DDR_DIE_CAP_4GBIT, /* die capacity */
62 MV_DDR_FREQ_SAR, /* frequency */
63 0, 0, /* cas_l cas_wl */
64 MV_DDR_TEMP_LOW, /* temperature */
65 MV_DDR_TIM_2T} }, /* timing */
66 BUS_MASK_32BIT_ECC, /* subphys mask */
67 MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
68 { {0} }, /* raw spd data */
69 {0} /* timing parameters */
70 };
71
mv_ddr_topology_map_get(void)72 struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
73 {
74 /* Return the board topology as defined in the board code */
75 return &board_topology_map;
76 }
77
board_early_init_f(void)78 int board_early_init_f(void)
79 {
80 /* Configure MPP */
81 writel(0x00001111, MVEBU_MPP_BASE + 0x00);
82 writel(0x00000000, MVEBU_MPP_BASE + 0x04);
83 writel(0x55000000, MVEBU_MPP_BASE + 0x08);
84 writel(0x55550550, MVEBU_MPP_BASE + 0x0c);
85 writel(0x55555555, MVEBU_MPP_BASE + 0x10);
86 writel(0x00100565, MVEBU_MPP_BASE + 0x14);
87 writel(0x40000000, MVEBU_MPP_BASE + 0x18);
88 writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
89
90 return 0;
91 }
92
spl_board_init(void)93 void spl_board_init(void)
94 {
95 }
96
board_init(void)97 int board_init(void)
98 {
99 /* address of boot parameters */
100 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
101
102 /* window for NVS */
103 mbus_dt_setup_win(&mbus_state, CONFIG_NVS_LOCATION, CONFIG_NVS_SIZE,
104 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS1);
105
106 /* DEV_READYn is not needed for NVS, ignore it when accessing CS1 */
107 writel(0x00004001, MVEBU_DEV_BUS_BASE + 0xc8);
108
109 spl_board_init();
110
111 return 0;
112 }
113
arch_preboot_os(void)114 void arch_preboot_os(void)
115 {
116 #ifdef CONFIG_WATCHDOG
117 wdt_stop(gd->watchdog_dev);
118 #endif
119 }
120
led_7seg_init(unsigned int segments)121 static int led_7seg_init(unsigned int segments)
122 {
123 int node;
124 int ret;
125 int i;
126 struct gpio_desc desc[8];
127
128 node = fdt_node_offset_by_compatible(gd->fdt_blob, 0,
129 "atl,of-led-7seg");
130 if (node < 0)
131 return -ENODEV;
132
133 ret = gpio_request_list_by_name_nodev(offset_to_ofnode(node),
134 "segment-gpios", desc,
135 ARRAY_SIZE(desc), GPIOD_IS_OUT);
136 if (ret < 0)
137 return ret;
138
139 for (i = 0; i < ARRAY_SIZE(desc); i++) {
140 ret = dm_gpio_set_value(&desc[i], !(segments & BIT(i)));
141 if (ret)
142 return ret;
143 }
144
145 return 0;
146 }
147
148 #ifdef CONFIG_MISC_INIT_R
misc_init_r(void)149 int misc_init_r(void)
150 {
151 static struct gpio_desc usb_en = {}, nand_wp = {}, phy_reset[2] = {},
152 led_en = {};
153
154 gpio_hog(&usb_en, "atl,usb-enable", "enable-gpio", 1);
155 gpio_hog(&nand_wp, "atl,nand-protect", "protect-gpio", 1);
156 gpio_hog_list(phy_reset, ARRAY_SIZE(phy_reset), "atl,phy-reset", "reset-gpio", 0);
157 gpio_hog(&led_en, "atl,led-enable", "enable-gpio", 1);
158
159 #ifdef MTDPARTS_MTDOOPS
160 env_set("mtdoops", MTDPARTS_MTDOOPS);
161 #endif
162
163 led_7seg_init(0xff);
164
165 return 0;
166 }
167 #endif
168
169 #ifdef CONFIG_DISPLAY_BOARDINFO
checkboard(void)170 int checkboard(void)
171 {
172 puts("Board: " CONFIG_SYS_BOARD "\n");
173
174 return 0;
175 }
176 #endif
177