1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright (C) 2013 Boundary Devices 4 */ 5/* ZQ Calibration */ 6DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003 7DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xa1390003 8DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F 9DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F 10DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F001F 11DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F 12/* 13 * DQS gating, read delay, write delay calibration values 14 * based on calibration compare of 0x00ffff00 15 */ 16DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x420E020E 17DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x02000200 18DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x42020202 19DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x01720172 20DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x494C4F4C 21DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4A4C4C49 22DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3F3F3133 23DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x39373F2E 24/* read data bit delay */ 25DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 26DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 27DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 28DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 29DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 30DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 31DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 32DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 33/* Complete calibration by forced measurment */ 34DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 35DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 36/* in DDR3, 64-bit mode, only MMDC0 is initiated */ 37DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002d 38DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030 39DATA 4, MX6_MMDC_P0_MDCFG0, 0x40445323 40DATA 4, MX6_MMDC_P0_MDCFG1, 0xb66e8c63 41DATA 4, MX6_MMDC_P0_MDCFG2, 0x01ff00db 42DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740 43DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 44DATA 4, MX6_MMDC_P0_MDRWD, 0x000026d2 45DATA 4, MX6_MMDC_P0_MDOR, 0x00440e21 46DATA 4, MX6_MMDC_P0_MDASP, 0x00000027 47DATA 4, MX6_MMDC_P0_MDCTL, 0x84190000 48/* MR2 */ 49DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032 50DATA 4, MX6_MMDC_P0_MDSCR, 0x0400803a 51/* MR3 */ 52DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 53DATA 4, MX6_MMDC_P0_MDSCR, 0x0000803b 54/* MR1 */ 55DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031 56DATA 4, MX6_MMDC_P0_MDSCR, 0x00428039 57/* MR0 */ 58DATA 4, MX6_MMDC_P0_MDSCR, 0x07208030 59DATA 4, MX6_MMDC_P0_MDSCR, 0x07208038 60/* ZQ calibration */ 61DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 62DATA 4, MX6_MMDC_P0_MDSCR, 0x04008048 63/* final ddr setup */ 64DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 65DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000007 66DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000007 67DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556d 68DATA 4, MX6_MMDC_P1_MAPSR, 0x00011006 69DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 70