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1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * (C) Copyright 2000-2003
4  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5  * modified by Wolfgang Wegner <w.wegner@astro-kom.de> for ASTRO 5373l
6  */
7 
8 #include <common.h>
9 #include <serial.h>
10 #include <watchdog.h>
11 #include <command.h>
12 #include <asm/m5329.h>
13 #include <asm/immap_5329.h>
14 #include <asm/io.h>
15 
16 /* needed for astro bus: */
17 #include <asm/uart.h>
18 #include "astro.h"
19 
20 DECLARE_GLOBAL_DATA_PTR;
21 extern void uart_port_conf(void);
22 
checkboard(void)23 int checkboard(void)
24 {
25 	puts("Board: ");
26 	puts("ASTRO MCF5373L (Urmel) Board\n");
27 	return 0;
28 }
29 
dram_init(void)30 int dram_init(void)
31 {
32 #if !defined(CONFIG_MONITOR_IS_IN_RAM)
33 	sdram_t *sdp = (sdram_t *)(MMAP_SDRAM);
34 
35 	/*
36 	 * GPIO configuration for bus should be set correctly from reset,
37 	 * so we do not care! First, set up address space: at this point,
38 	 * we should be running from internal SRAM;
39 	 * so use CONFIG_SYS_SDRAM_BASE as the base address for SDRAM,
40 	 * and do not care where it is
41 	 */
42 	__raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000018,
43 			&sdp->cs0);
44 	__raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000000,
45 			&sdp->cs1);
46 	/*
47 	 * I am not sure from the data sheet, but it seems burst length
48 	 * has to be 8 for the 16 bit data bus we use;
49 	 * so these values are for BL = 8
50 	 */
51 	__raw_writel(0x33211530, &sdp->cfg1);
52 	__raw_writel(0x56570000, &sdp->cfg2);
53 	/* send PrechargeALL, REF and IREF remain cleared! */
54 	__raw_writel(0xE1462C02, &sdp->ctrl);
55 	udelay(1);
56 	/* refresh SDRAM twice */
57 	__raw_writel(0xE1462C04, &sdp->ctrl);
58 	udelay(1);
59 	__raw_writel(0xE1462C04, &sdp->ctrl);
60 	/* init MR  */
61 	__raw_writel(0x008D0000, &sdp->mode);
62 	/* initialize EMR */
63 	__raw_writel(0x80010000, &sdp->mode);
64 	/* wait until DLL is locked */
65 	udelay(1);
66 	/*
67 	 * enable automatic refresh, lock mode register,
68 	 * clear iref and ipall
69 	 */
70 	__raw_writel(0x71462C00, &sdp->ctrl);
71 	/* Dummy write to start SDRAM */
72 	writel(0, CONFIG_SYS_SDRAM_BASE);
73 #endif
74 
75 	/*
76 	 * for get_ram_size() to work, both CS areas have to be
77 	 * configured, i.e. CS1 has to be explicitely disabled, else
78 	 * probing for memory will cause the SDRAM bus to hang!
79 	 * (Do not rely on the SDCS register(s) being set to 0x00000000
80 	 * during reset as stated in the data sheet.)
81 	 */
82 	gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
83 				0x80000000 - CONFIG_SYS_SDRAM_BASE);
84 
85 	return 0;
86 }
87 
88 #define UART_BASE MMAP_UART0
rs_serial_init(int port,int baud)89 int rs_serial_init(int port, int baud)
90 {
91 	uart_t *uart;
92 	u32 counter;
93 
94 	switch (port) {
95 	case 0:
96 		uart = (uart_t *)(MMAP_UART0);
97 		break;
98 	case 1:
99 		uart = (uart_t *)(MMAP_UART1);
100 		break;
101 	case 2:
102 		uart = (uart_t *)(MMAP_UART2);
103 		break;
104 	default:
105 		uart = (uart_t *)(MMAP_UART0);
106 	}
107 
108 	uart_port_conf();
109 
110 	/* write to SICR: SIM2 = uart mode,dcd does not affect rx */
111 	writeb(UART_UCR_RESET_RX, &uart->ucr);
112 	writeb(UART_UCR_RESET_TX, &uart->ucr);
113 	writeb(UART_UCR_RESET_ERROR, &uart->ucr);
114 	writeb(UART_UCR_RESET_MR, &uart->ucr);
115 	__asm__ ("nop");
116 
117 	writeb(0, &uart->uimr);
118 
119 	/* write to CSR: RX/TX baud rate from timers */
120 	writeb(UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK, &uart->ucsr);
121 
122 	writeb(UART_UMR_BC_8 | UART_UMR_PM_NONE, &uart->umr);
123 	writeb(UART_UMR_SB_STOP_BITS_1, &uart->umr);
124 
125 	/* Setting up BaudRate */
126 	counter = (u32) (gd->bus_clk / (baud));
127 	counter >>= 5;
128 
129 	/* write to CTUR: divide counter upper byte */
130 	writeb((u8) ((counter & 0xff00) >> 8), &uart->ubg1);
131 	/* write to CTLR: divide counter lower byte */
132 	writeb((u8) (counter & 0x00ff), &uart->ubg2);
133 
134 	writeb(UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED, &uart->ucr);
135 
136 	return 0;
137 }
138 
astro_put_char(char ch)139 void astro_put_char(char ch)
140 {
141 	uart_t *uart;
142 	unsigned long timer;
143 
144 	uart = (uart_t *)(MMAP_UART0);
145 	/*
146 	 * Wait for last character to go. Timeout of 6ms should
147 	 * be enough for our lowest baud rate of 2400.
148 	 */
149 	timer = get_timer(0);
150 	while (get_timer(timer) < 6) {
151 		if (readb(&uart->usr) & UART_USR_TXRDY)
152 			break;
153 	}
154 	writeb(ch, &uart->utb);
155 
156 	return;
157 }
158 
astro_is_char(void)159 int astro_is_char(void)
160 {
161 	uart_t *uart;
162 
163 	uart = (uart_t *)(MMAP_UART0);
164 	return readb(&uart->usr) & UART_USR_RXRDY;
165 }
166 
astro_get_char(void)167 int astro_get_char(void)
168 {
169 	uart_t *uart;
170 
171 	uart = (uart_t *)(MMAP_UART0);
172 	while (!(readb(&uart->usr) & UART_USR_RXRDY)) ;
173 	return readb(&uart->urb);
174 }
175 
misc_init_r(void)176 int misc_init_r(void)
177 {
178 	int retval = 0;
179 
180 	puts("Configure Xilinx FPGA...");
181 	retval = astro5373l_xilinx_load();
182 	if (!retval) {
183 		puts("failed!\n");
184 		return retval;
185 	}
186 	puts("done\n");
187 
188 	puts("Configure Altera FPGA...");
189 	retval = astro5373l_altera_load();
190 	if (!retval) {
191 		puts("failed!\n");
192 		return retval;
193 	}
194 	puts("done\n");
195 
196 	return retval;
197 }
198