1 /*
2 * Copyright (C) 2012 Renesas Solutions Corp.
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23 #include <common.h>
24 #include <init.h>
25 #include <malloc.h>
26 #include <asm/processor.h>
27 #include <asm/mach-types.h>
28 #include <asm/io.h>
29 #include <asm/arch/sys_proto.h>
30 #include <asm/gpio.h>
31 #include <asm/arch/rmobile.h>
32
33 #define s_init_wait(cnt) \
34 ({ \
35 volatile u32 i = 0x10000 * cnt; \
36 while (i > 0) \
37 i--; \
38 })
39
40 #define USBCR1 0xE605810A
41
s_init(void)42 void s_init(void)
43 {
44 struct r8a7740_rwdt *rwdt0 = (struct r8a7740_rwdt *)RWDT0_BASE;
45 struct r8a7740_rwdt *rwdt1 = (struct r8a7740_rwdt *)RWDT1_BASE;
46 struct r8a7740_cpg *cpg = (struct r8a7740_cpg *)CPG_BASE;
47 struct r8a7740_bsc *bsc = (struct r8a7740_bsc *)BSC_BASE;
48 struct r8a7740_ddrp *ddrp = (struct r8a7740_ddrp *)DDRP_BASE;
49 struct r8a7740_dbsc *dbsc = (struct r8a7740_dbsc *)DBSC_BASE;
50
51 /* Watchdog init */
52 writew(0xA500, &rwdt0->rwtcsra0);
53 writew(0xA500, &rwdt1->rwtcsra0);
54
55 /* CPG */
56 writel(0xFF800080, &cpg->rmstpcr4);
57 writel(0xFF800080, &cpg->smstpcr4);
58
59 /* USB clock */
60 writel(0x00000080, &cpg->usbckcr);
61 s_init_wait(1);
62
63 /* USBCR1 */
64 writew(0x0710, USBCR1);
65
66 /* FRQCR */
67 writel(0x00000000, &cpg->frqcrb);
68 writel(0x62030533, &cpg->frqcra);
69 writel(0x208A354E, &cpg->frqcrc);
70 writel(0x80331050, &cpg->frqcrb);
71 s_init_wait(1);
72
73 writel(0x00000000, &cpg->frqcrd);
74 s_init_wait(1);
75
76 /* SUBClk */
77 writel(0x0000010B, &cpg->subckcr);
78
79 /* PLL */
80 writel(0x00004004, &cpg->pllc01cr);
81 s_init_wait(1);
82
83 writel(0xa0000000, &cpg->pllc2cr);
84 s_init_wait(2);
85
86 /* BSC */
87 writel(0x0000001B, &bsc->cmncr);
88
89 writel(0x20000000, &dbsc->dbcmd);
90 writel(0x10009C40, &dbsc->dbcmd);
91 s_init_wait(1);
92
93 writel(0x00000007, &dbsc->dbkind);
94 writel(0x0E030A02, &dbsc->dbconf0);
95 writel(0x00000001, &dbsc->dbphytype);
96 writel(0x00000000, &dbsc->dbbl);
97 writel(0x00000006, &dbsc->dbtr0);
98 writel(0x00000005, &dbsc->dbtr1);
99 writel(0x00000000, &dbsc->dbtr2);
100 writel(0x00000006, &dbsc->dbtr3);
101 writel(0x00080006, &dbsc->dbtr4);
102 writel(0x00000015, &dbsc->dbtr5);
103 writel(0x0000000f, &dbsc->dbtr6);
104 writel(0x00000004, &dbsc->dbtr7);
105 writel(0x00000018, &dbsc->dbtr8);
106 writel(0x00000006, &dbsc->dbtr9);
107 writel(0x00000006, &dbsc->dbtr10);
108 writel(0x0000000F, &dbsc->dbtr11);
109 writel(0x0000000D, &dbsc->dbtr12);
110 writel(0x000000A0, &dbsc->dbtr13);
111 writel(0x000A0003, &dbsc->dbtr14);
112 writel(0x00000003, &dbsc->dbtr15);
113 writel(0x40005005, &dbsc->dbtr16);
114 writel(0x0C0C0000, &dbsc->dbtr17);
115 writel(0x00000200, &dbsc->dbtr18);
116 writel(0x00000040, &dbsc->dbtr19);
117 writel(0x00000001, &dbsc->dbrnk0);
118 writel(0x00000110, &dbsc->dbdficnt);
119 writel(0x00000101, &ddrp->funcctrl);
120 writel(0x00000001, &ddrp->dllctrl);
121 writel(0x00000186, &ddrp->zqcalctrl);
122 writel(0xB3440051, &ddrp->zqodtctrl);
123 writel(0x94449443, &ddrp->rdctrl);
124 writel(0x000000C0, &ddrp->rdtmg);
125 writel(0x00000101, &ddrp->fifoinit);
126 writel(0x02060506, &ddrp->outctrl);
127 writel(0x00004646, &ddrp->dqcalofs1);
128 writel(0x00004646, &ddrp->dqcalofs2);
129 writel(0x800000aa, &ddrp->dqcalexp);
130 writel(0x00000000, &ddrp->dllctrl);
131 writel(0x00000000, DDRPNCNT);
132
133 writel(0x0000000C, &dbsc->dbcmd);
134 readl(&dbsc->dbwait);
135 s_init_wait(1);
136
137 writel(0x00000002, DDRPNCNT);
138
139 writel(0x0000000C, &dbsc->dbcmd);
140 readl(&dbsc->dbwait);
141 s_init_wait(1);
142
143 writel(0x00000187, &ddrp->zqcalctrl);
144
145 writel(0x00009C40, &dbsc->dbcmd);
146 readl(&dbsc->dbwait);
147 s_init_wait(1);
148
149 writel(0x00009C40, &dbsc->dbcmd);
150 readl(&dbsc->dbwait);
151 s_init_wait(1);
152
153 writel(0x00000010, &dbsc->dbdficnt);
154 writel(0x02060507, &ddrp->outctrl);
155
156 writel(0x00009C40, &dbsc->dbcmd);
157 readl(&dbsc->dbwait);
158 s_init_wait(1);
159
160 writel(0x21009C40, &dbsc->dbcmd);
161 readl(&dbsc->dbwait);
162 s_init_wait(1);
163
164 writel(0x00009C40, &dbsc->dbcmd);
165 readl(&dbsc->dbwait);
166 s_init_wait(1);
167
168 writel(0x00009C40, &dbsc->dbcmd);
169 readl(&dbsc->dbwait);
170 s_init_wait(1);
171
172 writel(0x00009C40, &dbsc->dbcmd);
173 readl(&dbsc->dbwait);
174 s_init_wait(1);
175
176 writel(0x00009C40, &dbsc->dbcmd);
177 readl(&dbsc->dbwait);
178 s_init_wait(1);
179
180 writel(0x11000044, &dbsc->dbcmd);
181 readl(&dbsc->dbwait);
182 s_init_wait(1);
183
184 writel(0x2A000000, &dbsc->dbcmd);
185 readl(&dbsc->dbwait);
186 s_init_wait(1);
187
188 writel(0x2B000000, &dbsc->dbcmd);
189 readl(&dbsc->dbwait);
190
191 writel(0x29000004, &dbsc->dbcmd);
192 readl(&dbsc->dbwait);
193
194 writel(0x28001520, &dbsc->dbcmd);
195 readl(&dbsc->dbwait);
196 s_init_wait(1);
197
198 writel(0x03000200, &dbsc->dbcmd);
199 readl(&dbsc->dbwait);
200 s_init_wait(1);
201
202 writel(0x000001FF, &dbsc->dbrfcnf0);
203 writel(0x00010C30, &dbsc->dbrfcnf1);
204 writel(0x00000000, &dbsc->dbrfcnf2);
205
206 writel(0x00000001, &dbsc->dbrfen);
207 writel(0x00000001, &dbsc->dbacen);
208
209 /* BSC */
210 writel(0x00410400, &bsc->cs0bcr);
211 writel(0x00410400, &bsc->cs2bcr);
212 writel(0x00410400, &bsc->cs5bbcr);
213 writel(0x02CB0400, &bsc->cs6abcr);
214
215 writel(0x00000440, &bsc->cs0wcr);
216 writel(0x00000440, &bsc->cs2wcr);
217 writel(0x00000240, &bsc->cs5bwcr);
218 writel(0x00000240, &bsc->cs6awcr);
219
220 writel(0x00000005, &bsc->rbwtcnt);
221 writel(0x00000002, &bsc->cs0wcr2);
222 writel(0x00000002, &bsc->cs2wcr2);
223 writel(0x00000002, &bsc->cs4wcr2);
224 }
225
226 #define GPIO_ICCR (0xE60581A0)
227 #define ICCR_15BIT (1 << 15) /* any time 1 */
228 #define IIC0_CONTA (1 << 7)
229 #define IIC0_CONTB (1 << 6)
230 #define IIC1_CONTA (1 << 5)
231 #define IIC1_CONTB (1 << 4)
232 #define IIC0_PS33E (1 << 1)
233 #define IIC1_PS33E (1 << 0)
234 #define GPIO_ICCR_DATA \
235 (ICCR_15BIT | \
236 IIC0_CONTA | IIC0_CONTB | IIC1_CONTA | \
237 IIC1_CONTB | IIC0_PS33E | IIC1_PS33E)
238
239 #define MSTPCR1 0xE6150134
240 #define TMU0_MSTP125 (1 << 25)
241 #define I2C0_MSTP116 (1 << 16)
242
243 #define MSTPCR3 0xE615013C
244 #define I2C1_MSTP323 (1 << 23)
245 #define GETHER_MSTP309 (1 << 9)
246
247 #define GPIO_SCIFA1_TXD (0xE60520C4)
248 #define GPIO_SCIFA1_RXD (0xE60520C3)
249
board_early_init_f(void)250 int board_early_init_f(void)
251 {
252 /* TMU */
253 clrbits_le32(MSTPCR1, TMU0_MSTP125);
254
255 /* GETHER */
256 clrbits_le32(MSTPCR3, GETHER_MSTP309);
257
258 /* I2C 0/1 */
259 clrbits_le32(MSTPCR1, I2C0_MSTP116);
260 clrbits_le32(MSTPCR3, I2C1_MSTP323);
261
262 /* SCIFA1 */
263 writeb(1, GPIO_SCIFA1_TXD); /* SCIFA1_TXD */
264 writeb(1, GPIO_SCIFA1_RXD); /* SCIFA1_RXD */
265
266 /* IICCR */
267 writew(GPIO_ICCR_DATA, GPIO_ICCR);
268
269 return 0;
270 }
271
272 DECLARE_GLOBAL_DATA_PTR;
board_init(void)273 int board_init(void)
274 {
275 /* board id for linux */
276 gd->bd->bi_arch_number = MACH_TYPE_ARMADILLO800EVA;
277 /* adress of boot parameters */
278 gd->bd->bi_boot_params = ARMADILLO_800EVA_SDRAM_BASE + 0x100;
279
280 /* Init PFC controller */
281 r8a7740_pinmux_init();
282
283 /* GETHER Enable */
284 gpio_request(GPIO_FN_ET_CRS, NULL);
285 gpio_request(GPIO_FN_ET_MDC, NULL);
286 gpio_request(GPIO_FN_ET_MDIO, NULL);
287 gpio_request(GPIO_FN_ET_TX_ER, NULL);
288 gpio_request(GPIO_FN_ET_RX_ER, NULL);
289 gpio_request(GPIO_FN_ET_ERXD0, NULL);
290 gpio_request(GPIO_FN_ET_ERXD1, NULL);
291 gpio_request(GPIO_FN_ET_ERXD2, NULL);
292 gpio_request(GPIO_FN_ET_ERXD3, NULL);
293 gpio_request(GPIO_FN_ET_TX_CLK, NULL);
294 gpio_request(GPIO_FN_ET_TX_EN, NULL);
295 gpio_request(GPIO_FN_ET_ETXD0, NULL);
296 gpio_request(GPIO_FN_ET_ETXD1, NULL);
297 gpio_request(GPIO_FN_ET_ETXD2, NULL);
298 gpio_request(GPIO_FN_ET_ETXD3, NULL);
299 gpio_request(GPIO_FN_ET_PHY_INT, NULL);
300 gpio_request(GPIO_FN_ET_COL, NULL);
301 gpio_request(GPIO_FN_ET_RX_DV, NULL);
302 gpio_request(GPIO_FN_ET_RX_CLK, NULL);
303
304 gpio_request(GPIO_PORT18, NULL); /* PHY_RST */
305 gpio_direction_output(GPIO_PORT18, 1);
306
307 return 0;
308 }
309
dram_init(void)310 int dram_init(void)
311 {
312 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
313 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
314
315 return 0;
316 }
317
board_late_init(void)318 int board_late_init(void)
319 {
320 return 0;
321 }
322
reset_cpu(ulong addr)323 void reset_cpu(ulong addr)
324 {
325 }
326