1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2007-2008
4 * Stelian Pop <stelian@popies.net>
5 * Lead Tech Design <www.leadtechdesign.com>
6 */
7
8 #include <common.h>
9 #include <debug_uart.h>
10 #include <vsprintf.h>
11 #include <asm/io.h>
12 #include <asm/arch/at91sam9261.h>
13 #include <asm/arch/at91sam9261_matrix.h>
14 #include <asm/arch/at91sam9_smc.h>
15 #include <asm/arch/at91_common.h>
16 #include <asm/arch/at91_rstc.h>
17 #include <asm/arch/clk.h>
18 #include <asm/arch/gpio.h>
19 #include <lcd.h>
20 #include <atmel_lcdc.h>
21 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
22 #include <net.h>
23 #include <netdev.h>
24 #endif
25 #include <asm/mach-types.h>
26
27 DECLARE_GLOBAL_DATA_PTR;
28
29 /* ------------------------------------------------------------------------- */
30 /*
31 * Miscelaneous platform dependent initialisations
32 */
33
34 #ifdef CONFIG_CMD_NAND
at91sam9261ek_nand_hw_init(void)35 static void at91sam9261ek_nand_hw_init(void)
36 {
37 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
38 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
39 unsigned long csa;
40
41 /* Enable CS3 */
42 csa = readl(&matrix->ebicsa);
43 csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
44
45 writel(csa, &matrix->ebicsa);
46
47 /* Configure SMC CS3 for NAND/SmartMedia */
48 #ifdef CONFIG_AT91SAM9G10EK
49 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
50 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
51 &smc->cs[3].setup);
52 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(7) |
53 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(7),
54 &smc->cs[3].pulse);
55 writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
56 &smc->cs[3].cycle);
57 #else
58 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
59 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
60 &smc->cs[3].setup);
61 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
62 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
63 &smc->cs[3].pulse);
64 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
65 &smc->cs[3].cycle);
66 #endif
67 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
68 AT91_SMC_MODE_EXNW_DISABLE |
69 #ifdef CONFIG_SYS_NAND_DBW_16
70 AT91_SMC_MODE_DBW_16 |
71 #else /* CONFIG_SYS_NAND_DBW_8 */
72 AT91_SMC_MODE_DBW_8 |
73 #endif
74 AT91_SMC_MODE_TDF_CYCLE(2),
75 &smc->cs[3].mode);
76
77 at91_periph_clk_enable(ATMEL_ID_PIOC);
78
79 /* Configure RDY/BSY */
80 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
81
82 /* Enable NandFlash */
83 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
84
85 at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */
86 at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */
87 }
88 #endif
89
90 #ifdef CONFIG_DRIVER_DM9000
at91sam9261ek_dm9000_hw_init(void)91 static void at91sam9261ek_dm9000_hw_init(void)
92 {
93 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
94
95 /* Configure SMC CS2 for DM9000 */
96 #ifdef CONFIG_AT91SAM9G10EK
97 writel(AT91_SMC_SETUP_NWE(3) | AT91_SMC_SETUP_NCS_WR(0) |
98 AT91_SMC_SETUP_NRD(3) | AT91_SMC_SETUP_NCS_RD(0),
99 &smc->cs[2].setup);
100 writel(AT91_SMC_PULSE_NWE(6) | AT91_SMC_PULSE_NCS_WR(8) |
101 AT91_SMC_PULSE_NRD(6) | AT91_SMC_PULSE_NCS_RD(8),
102 &smc->cs[2].pulse);
103 writel(AT91_SMC_CYCLE_NWE(20) | AT91_SMC_CYCLE_NRD(20),
104 &smc->cs[2].cycle);
105 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
106 AT91_SMC_MODE_EXNW_DISABLE |
107 AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
108 AT91_SMC_MODE_TDF_CYCLE(1),
109 &smc->cs[2].mode);
110 #else
111 writel(AT91_SMC_SETUP_NWE(3) | AT91_SMC_SETUP_NCS_WR(0) |
112 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
113 &smc->cs[2].setup);
114 writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(8) |
115 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(8),
116 &smc->cs[2].pulse);
117 writel(AT91_SMC_CYCLE_NWE(16) | AT91_SMC_CYCLE_NRD(16),
118 &smc->cs[2].cycle);
119 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
120 AT91_SMC_MODE_EXNW_DISABLE |
121 AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
122 AT91_SMC_MODE_TDF_CYCLE(1),
123 &smc->cs[2].mode);
124 #endif
125
126 /* Configure Reset signal as output */
127 at91_set_gpio_output(AT91_PIN_PC10, 0);
128
129 /* Configure Interrupt pin as input, no pull-up */
130 at91_set_gpio_input(AT91_PIN_PC11, 0);
131 }
132 #endif
133
134 #ifdef CONFIG_LCD
135 vidinfo_t panel_info = {
136 .vl_col = 240,
137 .vl_row = 320,
138 .vl_clk = 4965000,
139 .vl_sync = ATMEL_LCDC_INVLINE_INVERTED |
140 ATMEL_LCDC_INVFRAME_INVERTED,
141 .vl_bpix = 3,
142 .vl_tft = 1,
143 .vl_hsync_len = 5,
144 .vl_left_margin = 1,
145 .vl_right_margin = 33,
146 .vl_vsync_len = 1,
147 .vl_upper_margin = 1,
148 .vl_lower_margin = 0,
149 .mmio = ATMEL_BASE_LCDC,
150 };
151
lcd_enable(void)152 void lcd_enable(void)
153 {
154 at91_set_gpio_value(AT91_PIN_PA12, 0); /* power up */
155 }
156
lcd_disable(void)157 void lcd_disable(void)
158 {
159 at91_set_gpio_value(AT91_PIN_PA12, 1); /* power down */
160 }
161
at91sam9261ek_lcd_hw_init(void)162 static void at91sam9261ek_lcd_hw_init(void)
163 {
164 at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */
165 at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */
166 at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */
167 at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */
168 at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */
169 at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */
170 at91_set_A_periph(AT91_PIN_PB9, 0); /* LCDD4 */
171 at91_set_A_periph(AT91_PIN_PB10, 0); /* LCDD5 */
172 at91_set_A_periph(AT91_PIN_PB11, 0); /* LCDD6 */
173 at91_set_A_periph(AT91_PIN_PB12, 0); /* LCDD7 */
174 at91_set_A_periph(AT91_PIN_PB15, 0); /* LCDD10 */
175 at91_set_A_periph(AT91_PIN_PB16, 0); /* LCDD11 */
176 at91_set_A_periph(AT91_PIN_PB17, 0); /* LCDD12 */
177 at91_set_A_periph(AT91_PIN_PB18, 0); /* LCDD13 */
178 at91_set_A_periph(AT91_PIN_PB19, 0); /* LCDD14 */
179 at91_set_A_periph(AT91_PIN_PB20, 0); /* LCDD15 */
180 at91_set_B_periph(AT91_PIN_PB23, 0); /* LCDD18 */
181 at91_set_B_periph(AT91_PIN_PB24, 0); /* LCDD19 */
182 at91_set_B_periph(AT91_PIN_PB25, 0); /* LCDD20 */
183 at91_set_B_periph(AT91_PIN_PB26, 0); /* LCDD21 */
184 at91_set_B_periph(AT91_PIN_PB27, 0); /* LCDD22 */
185 at91_set_B_periph(AT91_PIN_PB28, 0); /* LCDD23 */
186
187 at91_system_clk_enable(AT91_PMC_HCK1);
188
189 /* For 9G10EK, let U-Boot allocate the framebuffer in SDRAM */
190 #ifdef CONFIG_AT91SAM9261EK
191 gd->fb_base = ATMEL_BASE_SRAM;
192 #endif
193 }
194
195 #ifdef CONFIG_LCD_INFO
196 #include <nand.h>
197 #include <version.h>
198
lcd_show_board_info(void)199 void lcd_show_board_info(void)
200 {
201 ulong dram_size, nand_size;
202 int i;
203 char temp[32];
204
205 lcd_printf ("%s\n", U_BOOT_VERSION);
206 lcd_printf ("(C) 2008 ATMEL Corp\n");
207 lcd_printf ("at91support@atmel.com\n");
208 lcd_printf ("%s CPU at %s MHz\n",
209 ATMEL_CPU_NAME,
210 strmhz(temp, get_cpu_clk_rate()));
211
212 dram_size = 0;
213 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
214 dram_size += gd->bd->bi_dram[i].size;
215 nand_size = 0;
216 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
217 nand_size += get_nand_dev_by_index(i)->size;
218 lcd_printf (" %ld MB SDRAM, %ld MB NAND\n",
219 dram_size >> 20,
220 nand_size >> 20 );
221 }
222 #endif /* CONFIG_LCD_INFO */
223 #endif
224
225 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
board_debug_uart_init(void)226 void board_debug_uart_init(void)
227 {
228 at91_seriald_hw_init();
229 }
230 #endif
231
232 #ifdef CONFIG_BOARD_EARLY_INIT_F
board_early_init_f(void)233 int board_early_init_f(void)
234 {
235 #ifdef CONFIG_DEBUG_UART
236 debug_uart_init();
237 #endif
238 return 0;
239 }
240 #endif
241
board_init(void)242 int board_init(void)
243 {
244 #ifdef CONFIG_AT91SAM9G10EK
245 /* arch number of AT91SAM9G10EK-Board */
246 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G10EK;
247 #else
248 /* arch number of AT91SAM9261EK-Board */
249 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9261EK;
250 #endif
251 /* adress of boot parameters */
252 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
253
254 #ifdef CONFIG_CMD_NAND
255 at91sam9261ek_nand_hw_init();
256 #endif
257 #ifdef CONFIG_DRIVER_DM9000
258 at91sam9261ek_dm9000_hw_init();
259 #endif
260 #ifdef CONFIG_LCD
261 at91sam9261ek_lcd_hw_init();
262 #endif
263 return 0;
264 }
265
266 #ifdef CONFIG_DRIVER_DM9000
board_eth_init(bd_t * bis)267 int board_eth_init(bd_t *bis)
268 {
269 return dm9000_initialize(bis);
270 }
271 #endif
272
dram_init(void)273 int dram_init(void)
274 {
275 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
276 CONFIG_SYS_SDRAM_SIZE);
277
278 return 0;
279 }
280
281 #ifdef CONFIG_RESET_PHY_R
reset_phy(void)282 void reset_phy(void)
283 {
284 #ifdef CONFIG_DRIVER_DM9000
285 /*
286 * Initialize ethernet HW addr prior to starting Linux,
287 * needed for nfsroot
288 */
289 eth_init();
290 #endif
291 }
292 #endif
293