1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
4 *
5 * Based on: gw_ventana_spl.c which is:
6 * Copyright (C) 2014 Gateworks Corporation
7 */
8
9 #include <common.h>
10 #include <i2c.h>
11 #include <asm/io.h>
12 #include <asm/arch/iomux.h>
13 #include <asm/arch/mx6-ddr.h>
14 #include <asm/arch/mx6-pins.h>
15 #include <asm/arch/sys_proto.h>
16 #include <asm/mach-imx/boot_mode.h>
17 #include <asm/mach-imx/iomux-v3.h>
18 #include <asm/mach-imx/mxc_i2c.h>
19 #include <spl.h>
20
21 #include "platinum.h"
22
23 #undef RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */
24
25 /* Configure MX6Q/DUAL mmdc DDR io registers */
26 struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
27 /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
28 .dram_sdclk_0 = 0x00020030,
29 .dram_sdclk_1 = 0x00020030,
30 .dram_cas = 0x00020030,
31 .dram_ras = 0x00020030,
32 .dram_reset = 0x00020030,
33 /* SDCKE[0:1]: 100k pull-up */
34 .dram_sdcke0 = 0x00003000,
35 .dram_sdcke1 = 0x00003000,
36 /* SDBA2: pull-up disabled */
37 .dram_sdba2 = 0x00000000,
38 /* SDODT[0:1]: 100k pull-up, 40 ohm */
39 .dram_sdodt0 = 0x00003030,
40 .dram_sdodt1 = 0x00003030,
41 /* SDQS[0:7]: Differential input, 40 ohm */
42 .dram_sdqs0 = 0x00000030,
43 .dram_sdqs1 = 0x00000030,
44 .dram_sdqs2 = 0x00000030,
45 .dram_sdqs3 = 0x00000030,
46 .dram_sdqs4 = 0x00000030,
47 .dram_sdqs5 = 0x00000030,
48 .dram_sdqs6 = 0x00000030,
49 .dram_sdqs7 = 0x00000030,
50 /* DQM[0:7]: Differential input, 40 ohm */
51 .dram_dqm0 = 0x00020030,
52 .dram_dqm1 = 0x00020030,
53 .dram_dqm2 = 0x00020030,
54 .dram_dqm3 = 0x00020030,
55 .dram_dqm4 = 0x00020030,
56 .dram_dqm5 = 0x00020030,
57 .dram_dqm6 = 0x00020030,
58 .dram_dqm7 = 0x00020030,
59 };
60
61 /* Configure MX6Q/DUAL mmdc GRP io registers */
62 struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
63 /* DDR3 */
64 .grp_ddr_type = 0x000c0000,
65 .grp_ddrmode_ctl = 0x00020000,
66 /* disable DDR pullups */
67 .grp_ddrpke = 0x00000000,
68 /* ADDR[00:16], SDBA[0:1]: 40 ohm */
69 .grp_addds = 0x00000030,
70 /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
71 .grp_ctlds = 0x00000030,
72 /* DATA[00:63]: Differential input, 40 ohm */
73 .grp_ddrmode = 0x00020000,
74 .grp_b0ds = 0x00000030,
75 .grp_b1ds = 0x00000030,
76 .grp_b2ds = 0x00000030,
77 .grp_b3ds = 0x00000030,
78 .grp_b4ds = 0x00000030,
79 .grp_b5ds = 0x00000030,
80 .grp_b6ds = 0x00000030,
81 .grp_b7ds = 0x00000030,
82 };
83
84 /* MT41J128M16JT-125 */
85 static struct mx6_ddr3_cfg mt41j128m16jt_125 = {
86 .mem_speed = 1600,
87 .density = 2,
88 .width = 16,
89 .banks = 8,
90 .rowaddr = 14,
91 .coladdr = 10,
92 .pagesz = 2,
93 .trcd = 1375,
94 .trcmin = 4875,
95 .trasmin = 3500,
96 };
97
98 static struct mx6_mmdc_calibration mx6dq_mmdc_calib = {
99 /* Write leveling calibration determine */
100 .p0_mpwldectrl0 = 0x001f001f,
101 .p0_mpwldectrl1 = 0x001f001f,
102 .p1_mpwldectrl0 = 0x00440044,
103 .p1_mpwldectrl1 = 0x00440044,
104 /* Read DQS Gating calibration */
105 .p0_mpdgctrl0 = 0x434b0350,
106 .p0_mpdgctrl1 = 0x034c0359,
107 .p1_mpdgctrl0 = 0x434b0350,
108 .p1_mpdgctrl1 = 0x03650348,
109 /* Read Calibration: DQS delay relative to DQ read access */
110 .p0_mprddlctl = 0x4436383b,
111 .p1_mprddlctl = 0x39393341,
112 /* Write Calibration: DQ/DM delay relative to DQS write access */
113 .p0_mpwrdlctl = 0x35373933,
114 .p1_mpwrdlctl = 0x48254a36,
115 };
116
spl_dram_init(int width)117 static void spl_dram_init(int width)
118 {
119 struct mx6_ddr3_cfg *mem = &mt41j128m16jt_125;
120 struct mx6_ddr_sysinfo sysinfo = {
121 /* width of data bus:0=16,1=32,2=64 */
122 .dsize = width / 32,
123 /* config for full 4GB range so that get_mem_size() works */
124 .cs_density = 32, /* 32Gb per CS */
125 /* single chip select */
126 .ncs = 1,
127 .cs1_mirror = 1,
128 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
129 #ifdef RTT_NOM_120OHM
130 .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */
131 #else
132 .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
133 #endif
134 .walat = 0, /* Write additional latency */
135 .ralat = 5, /* Read additional latency */
136 .mif3_mode = 3, /* Command prediction working mode */
137 .bi_on = 1, /* Bank interleaving enabled */
138 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
139 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
140 .ddr_type = DDR_TYPE_DDR3,
141 .refsel = 1, /* Refresh cycles at 32KHz */
142 .refr = 7, /* 8 refresh commands per refresh cycle */
143 };
144
145 mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
146 mx6_dram_cfg(&sysinfo, &mx6dq_mmdc_calib, mem);
147 }
148
149 /*
150 * Called from C runtime startup code (arch/arm/lib/crt0.S:_main)
151 * - we have a stack and a place to store GD, both in SRAM
152 * - no variable global data is available
153 */
board_init_f(ulong dummy)154 void board_init_f(ulong dummy)
155 {
156 /* Setup AIPS and disable watchdog */
157 arch_cpu_init();
158
159 ccgr_init();
160 gpr_init();
161
162 /* UART iomux */
163 board_early_init_f();
164
165 /* Setup GP timer */
166 timer_init();
167
168 /* UART clocks enabled and gd valid - init serial console */
169 preloader_console_init();
170
171 /* Init DDR with 32bit width */
172 spl_dram_init(32);
173
174 /* Clear the BSS */
175 memset(__bss_start, 0, __bss_end - __bss_start);
176
177 /*
178 * Setup enet related MUXing early to give the PHY
179 * some time to wake-up from reset
180 */
181 platinum_setup_enet();
182
183 /* load/boot image from boot device */
184 board_init_r(NULL, 0);
185 }
186