1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2015 Beckhoff Automation GmbH & Co. KG
4 * Patrick Bruenn <p.bruenn@beckhoff.com>
5 *
6 * Based on <u-boot>/board/freescale/mx53loco/mx53loco.c
7 * Copyright (C) 2011 Freescale Semiconductor, Inc.
8 */
9
10 #include <common.h>
11 #include <cpu_func.h>
12 #include <init.h>
13 #include <asm/arch/sys_proto.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/iomux-mx53.h>
16 #include <asm/mach-imx/mx5_video.h>
17 #include <ACEX1K.h>
18 #include <asm/gpio.h>
19
20 enum LED_GPIOS {
21 GPIO_SD1_CD = IMX_GPIO_NR(1, 1),
22 GPIO_SD2_CD = IMX_GPIO_NR(1, 4),
23 GPIO_LED_SD2_R = IMX_GPIO_NR(3, 16),
24 GPIO_LED_SD2_B = IMX_GPIO_NR(3, 17),
25 GPIO_LED_SD2_G = IMX_GPIO_NR(3, 18),
26 GPIO_LED_SD1_R = IMX_GPIO_NR(3, 19),
27 GPIO_LED_SD1_B = IMX_GPIO_NR(3, 20),
28 GPIO_LED_SD1_G = IMX_GPIO_NR(3, 21),
29 GPIO_LED_PWR_R = IMX_GPIO_NR(3, 22),
30 GPIO_LED_PWR_B = IMX_GPIO_NR(3, 23),
31 GPIO_LED_PWR_G = IMX_GPIO_NR(3, 24),
32 GPIO_SUPS_INT = IMX_GPIO_NR(3, 31),
33 GPIO_C3_CONFIG = IMX_GPIO_NR(6, 8),
34 GPIO_C3_STATUS = IMX_GPIO_NR(6, 7),
35 GPIO_C3_DONE = IMX_GPIO_NR(6, 9),
36 };
37
38 #define CCAT_BASE_ADDR ((void *)0xf0000000)
39 #define CCAT_END_ADDR (CCAT_BASE_ADDR + (1024 * 1024 * 32))
40 #define CCAT_SIZE 1191788
41 #define CCAT_SIGN_ADDR (CCAT_BASE_ADDR + 12)
42 static const char CCAT_SIGNATURE[] = "CCAT";
43
44 static const u32 CCAT_MODE_CONFIG = 0x0024DC81;
45 static const u32 CCAT_MODE_RUN = 0x0033DC8F;
46
47 DECLARE_GLOBAL_DATA_PTR;
48
get_board_rev(void)49 u32 get_board_rev(void)
50 {
51 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
52 struct fuse_bank *bank = &iim->bank[0];
53 struct fuse_bank0_regs *fuse =
54 (struct fuse_bank0_regs *)bank->fuse_regs;
55
56 int rev = readl(&fuse->gp[6]);
57
58 return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
59 }
60
61 /*
62 * Set CCAT mode
63 * @mode: use CCAT_MODE_CONFIG or CCAT_MODE_RUN
64 */
weim_cs0_settings(u32 mode)65 void weim_cs0_settings(u32 mode)
66 {
67 struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
68
69 writel(0x0, &weim_regs->cs0gcr1);
70 writel(mode, &weim_regs->cs0gcr1);
71 writel(0x00001002, &weim_regs->cs0gcr2);
72
73 writel(0x04000000, &weim_regs->cs0rcr1);
74 writel(0x00000000, &weim_regs->cs0rcr2);
75
76 writel(0x04000000, &weim_regs->cs0wcr1);
77 writel(0x00000000, &weim_regs->cs0wcr2);
78 }
79
setup_gpio_eim(void)80 static void setup_gpio_eim(void)
81 {
82 gpio_request(GPIO_C3_STATUS, "GPIO_C3_STATUS");
83 gpio_request(GPIO_C3_DONE, "GPIO_C3_DONE");
84 gpio_request(GPIO_C3_CONFIG, "GPIO_C3_CONFIG");
85 gpio_direction_input(GPIO_C3_STATUS);
86 gpio_direction_input(GPIO_C3_DONE);
87 gpio_direction_output(GPIO_C3_CONFIG, 1);
88
89 weim_cs0_settings(CCAT_MODE_RUN);
90 }
91
setup_gpio_sups(void)92 static void setup_gpio_sups(void)
93 {
94 gpio_request(GPIO_SUPS_INT, "GPIO_SUPS_INT");
95 gpio_direction_input(GPIO_SUPS_INT);
96
97 static const int BLINK_INTERVALL = 50000;
98 int status = 1;
99 while (gpio_get_value(GPIO_SUPS_INT)) {
100 /* signal "CX SUPS power fail" */
101 gpio_set_value(GPIO_LED_PWR_R,
102 (++status / BLINK_INTERVALL) % 2);
103 }
104
105 /* signal "CX power up" */
106 gpio_set_value(GPIO_LED_PWR_R, 1);
107 }
108
setup_gpio_leds(void)109 static void setup_gpio_leds(void)
110 {
111 gpio_request(GPIO_LED_SD2_R, "GPIO_LED_SD2_R");
112 gpio_request(GPIO_LED_SD2_B, "GPIO_LED_SD2_B");
113 gpio_request(GPIO_LED_SD2_G, "GPIO_LED_SD2_G");
114 gpio_request(GPIO_LED_SD1_R, "GPIO_LED_SD1_R");
115 gpio_request(GPIO_LED_SD1_B, "GPIO_LED_SD1_B");
116 gpio_request(GPIO_LED_SD1_G, "GPIO_LED_SD1_G");
117 gpio_request(GPIO_LED_PWR_R, "GPIO_LED_PWR_R");
118 gpio_request(GPIO_LED_PWR_B, "GPIO_LED_PWR_B");
119 gpio_request(GPIO_LED_PWR_G, "GPIO_LED_PWR_G");
120
121 gpio_direction_output(GPIO_LED_SD2_R, 0);
122 gpio_direction_output(GPIO_LED_SD2_B, 0);
123 gpio_direction_output(GPIO_LED_SD2_G, 0);
124 gpio_direction_output(GPIO_LED_SD1_R, 0);
125 gpio_direction_output(GPIO_LED_SD1_B, 0);
126 gpio_direction_output(GPIO_LED_SD1_G, 0);
127 gpio_direction_output(GPIO_LED_PWR_R, 0);
128 gpio_direction_output(GPIO_LED_PWR_B, 0);
129 gpio_direction_output(GPIO_LED_PWR_G, 0);
130 }
131
132 #ifdef CONFIG_USB_EHCI_MX5
board_ehci_hcd_init(int port)133 int board_ehci_hcd_init(int port)
134 {
135 /* request VBUS power enable pin, GPIO7_8 */
136 gpio_direction_output(IMX_GPIO_NR(7, 8), 1);
137 return 0;
138 }
139 #endif
140
141
power_init(void)142 static int power_init(void)
143 {
144 /* nothing to do on CX9020 */
145 return 0;
146 }
147
clock_1GHz(void)148 static void clock_1GHz(void)
149 {
150 int ret;
151 u32 ref_clk = MXC_HCLK;
152 /*
153 * After increasing voltage to 1.25V, we can switch
154 * CPU clock to 1GHz and DDR to 400MHz safely
155 */
156 ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK);
157 if (ret)
158 printf("CPU: Switch CPU clock to 1GHZ failed\n");
159
160 ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
161 ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
162 if (ret)
163 printf("CPU: Switch DDR clock to 400MHz failed\n");
164 }
165
board_early_init_f(void)166 int board_early_init_f(void)
167 {
168
169 return 0;
170 }
171
board_init(void)172 int board_init(void)
173 {
174 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
175
176 mxc_set_sata_internal_clock();
177
178 setup_gpio_leds();
179 setup_gpio_sups();
180 setup_gpio_eim();
181 setup_iomux_lcd();
182
183 return 0;
184 }
185
checkboard(void)186 int checkboard(void)
187 {
188 puts("Board: Beckhoff CX9020\n");
189
190 return 0;
191 }
192
ccat_config_fn(int assert_config,int flush,int cookie)193 static int ccat_config_fn(int assert_config, int flush, int cookie)
194 {
195 /* prepare FPGA for programming */
196 weim_cs0_settings(CCAT_MODE_CONFIG);
197 gpio_set_value(GPIO_C3_CONFIG, 0);
198 udelay(1);
199 gpio_set_value(GPIO_C3_CONFIG, 1);
200 udelay(230);
201
202 return FPGA_SUCCESS;
203 }
204
ccat_status_fn(int cookie)205 static int ccat_status_fn(int cookie)
206 {
207 return FPGA_FAIL;
208 }
209
ccat_write_fn(const void * buf,size_t buf_len,int flush,int cookie)210 static int ccat_write_fn(const void *buf, size_t buf_len, int flush, int cookie)
211 {
212 const uint8_t *const buffer = buf;
213
214 /* program CCAT */
215 int i;
216 for (i = 0; i < buf_len; ++i)
217 writeb(buffer[i], CCAT_BASE_ADDR);
218
219 writeb(0xff, CCAT_BASE_ADDR);
220 writeb(0xff, CCAT_BASE_ADDR);
221
222 return FPGA_SUCCESS;
223 }
224
ccat_done_fn(int cookie)225 static int ccat_done_fn(int cookie)
226 {
227 /* programming complete? */
228 return gpio_get_value(GPIO_C3_DONE);
229 }
230
ccat_post_fn(int cookie)231 static int ccat_post_fn(int cookie)
232 {
233 /* switch to FPGA run mode */
234 weim_cs0_settings(CCAT_MODE_RUN);
235 invalidate_dcache_range((ulong) CCAT_BASE_ADDR, (ulong) CCAT_END_ADDR);
236
237 if (memcmp(CCAT_SIGN_ADDR, CCAT_SIGNATURE, sizeof(CCAT_SIGNATURE))) {
238 printf("Verifing CCAT firmware failed, signature not found\n");
239 return FPGA_FAIL;
240 }
241
242 /* signal "CX booting OS" */
243 gpio_set_value(GPIO_LED_PWR_R, 1);
244 gpio_set_value(GPIO_LED_PWR_G, 1);
245 gpio_set_value(GPIO_LED_PWR_B, 0);
246 return FPGA_SUCCESS;
247 }
248
249 static Altera_CYC2_Passive_Serial_fns ccat_fns = {
250 .config = ccat_config_fn,
251 .status = ccat_status_fn,
252 .done = ccat_done_fn,
253 .write = ccat_write_fn,
254 .abort = ccat_post_fn,
255 .post = ccat_post_fn,
256 };
257
258 static Altera_desc ccat_fpga = {
259 .family = Altera_CYC2,
260 .iface = passive_serial,
261 .size = CCAT_SIZE,
262 .iface_fns = &ccat_fns,
263 .base = CCAT_BASE_ADDR,
264 };
265
board_late_init(void)266 int board_late_init(void)
267 {
268 if (!power_init())
269 clock_1GHz();
270
271 fpga_init();
272 fpga_add(fpga_altera, &ccat_fpga);
273
274 return 0;
275 }
276