1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2018 Simone CIANNI <simone.cianni@bticino.it>
4 * Copyright (C) 2018 Raffaele RECALCATI <raffaele.recalcati@bticino.it>
5 * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
6 */
7
8 #include <common.h>
9 #include <serial.h>
10 #include <spl.h>
11
12 #include <asm/io.h>
13 #include <linux/sizes.h>
14
15 #include <asm/arch/clock.h>
16 #include <asm/arch/crm_regs.h>
17 #include <asm/arch/iomux.h>
18 #include <asm/arch/mx6-ddr.h>
19 #include <asm/arch/mx6-pins.h>
20 #include <asm/arch/sys_proto.h>
21
22 DECLARE_GLOBAL_DATA_PTR;
23
24 #define IMX6SDL_DRIVE_STRENGTH 0x28
25 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
26 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
27
28 static iomux_v3_cfg_t const uart3_pads[] = {
29 IOMUX_PADS(PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
30 IOMUX_PADS(PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
31 };
32
33 #ifdef CONFIG_SPL_OS_BOOT
spl_start_uboot(void)34 int spl_start_uboot(void)
35 {
36 /* break into full u-boot on 'c' */
37 if (serial_tstc() && serial_getc() == 'c')
38 return 1;
39
40 return 0;
41 }
42 #endif
43
44 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
45 .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
46 .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
47 .dram_cas = IMX6SDL_DRIVE_STRENGTH,
48 .dram_ras = IMX6SDL_DRIVE_STRENGTH,
49 .dram_reset = IMX6SDL_DRIVE_STRENGTH,
50 .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
51 .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
52 .dram_sdba2 = 0x00000000,
53 .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
54 .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
55 .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
56 .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
57 .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
58 .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
59 .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
60 .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
61 .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
62 .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
63 .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
64 .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
65 .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
66 .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
67 .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
68 .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
69 .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
70 .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
71 };
72
73 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
74 .grp_ddr_type = 0x000c0000,
75 .grp_ddrmode_ctl = 0x00020000,
76 .grp_ddrpke = 0x00000000,
77 .grp_addds = IMX6SDL_DRIVE_STRENGTH,
78 .grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
79 .grp_ddrmode = 0x00020000,
80 .grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
81 .grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
82 .grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
83 .grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
84 .grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
85 .grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
86 .grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
87 .grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
88 };
89
90 static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
91 .mem_speed = 1600,
92 .density = 4,
93 .width = 32,
94 .banks = 8,
95 .rowaddr = 14,
96 .coladdr = 10,
97 .pagesz = 2,
98 .trcd = 1375,
99 .trcmin = 4875,
100 .trasmin = 3500,
101 .SRT = 0,
102 };
103
104 static struct mx6_mmdc_calibration mx6dl_mmdc_calib = {
105 .p0_mpwldectrl0 = 0x0042004b,
106 .p0_mpwldectrl1 = 0x0038003c,
107 .p0_mpdgctrl0 = 0x42340230,
108 .p0_mpdgctrl1 = 0x0228022c,
109 .p0_mprddlctl = 0x42444646,
110 .p0_mpwrdlctl = 0x38382e2e,
111 };
112
113 static struct mx6_ddr_sysinfo mem_dl = {
114 .dsize = 1,
115 .cs1_mirror = 0,
116 /* config for full 4GB range so that get_mem_size() works */
117 .cs_density = 32,
118 .ncs = 1,
119 .bi_on = 1,
120 .rtt_nom = 1,
121 .rtt_wr = 1,
122 .ralat = 5,
123 .walat = 0,
124 .mif3_mode = 3,
125 .rst_to_cke = 0x23,
126 .sde_to_rst = 0x10,
127 .refsel = 1,
128 .refr = 7,
129 };
130
spl_dram_init(void)131 static void spl_dram_init(void)
132 {
133 mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
134 mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41k128m16jt_125);
135
136 udelay(100);
137 }
138
ccgr_init(void)139 static void ccgr_init(void)
140 {
141 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
142
143 writel(0x00003f3f, &ccm->CCGR0);
144 writel(0x0030fc00, &ccm->CCGR1);
145 writel(0x000fc000, &ccm->CCGR2);
146 writel(0x3f300000, &ccm->CCGR3);
147 writel(0xff00f300, &ccm->CCGR4);
148 writel(0x0f0000c3, &ccm->CCGR5);
149 writel(0x000003cc, &ccm->CCGR6);
150 }
151
board_init_f(ulong dummy)152 void board_init_f(ulong dummy)
153 {
154 ccgr_init();
155
156 /* setup AIPS and disable watchdog */
157 arch_cpu_init();
158
159 gpr_init();
160
161 /* iomux */
162 SETUP_IOMUX_PADS(uart3_pads);
163
164 /* setup GP timer */
165 timer_init();
166
167 /* UART clocks enabled and gd valid - init serial console */
168 preloader_console_init();
169
170 /* DDR initialization */
171 spl_dram_init();
172 }
173