1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2011
4 * egnite GmbH <info@egnite.de>
5 *
6 * (C) Copyright 2010
7 * Ole Reinhardt <ole.reinhardt@thermotemp.de>
8 */
9
10 /*
11 * Ethernut 5 general board support
12 *
13 * Ethernut is an open source hardware and software project for
14 * embedded Ethernet devices. Hardware layouts and CAD files are
15 * freely available under BSD-like license.
16 *
17 * Ethernut 5 is the first member of the Ethernut board family
18 * with U-Boot and Linux support. This implementation is based
19 * on the original work done by Ole Reinhardt, but heavily modified
20 * to support additional features and the latest board revision 5.0F.
21 *
22 * Main board components are by default:
23 *
24 * Atmel AT91SAM9XE512 CPU with 512 kBytes NOR Flash
25 * 2 x 64 MBytes Micron MT48LC32M16A2P SDRAM
26 * 512 MBytes Micron MT29F4G08ABADA NAND Flash
27 * 4 MBytes Atmel AT45DB321D DataFlash
28 * SMSC LAN8710 Ethernet PHY
29 * Atmel ATmega168 MCU used for power management
30 * Linear Technology LTC4411 PoE controller
31 *
32 * U-Boot relevant board interfaces are:
33 *
34 * 100 Mbit Ethernet with IEEE 802.3af PoE
35 * RS-232 serial port
36 * USB host and device
37 * MMC/SD-Card slot
38 * Expansion port with I2C, SPI and more...
39 *
40 * Typically the U-Boot image is loaded from serial DataFlash into
41 * SDRAM by the samboot boot loader, which is located in internal
42 * NOR Flash and provides all essential initializations like CPU
43 * and peripheral clocks and, of course, the SDRAM configuration.
44 *
45 * For testing purposes it is also possibly to directly transfer
46 * the image into SDRAM via JTAG. A tested configuration exists
47 * for the Turtelizer 2 hardware dongle and the OpenOCD software.
48 * In this case the latter will do the basic hardware configuration
49 * via its reset-init script.
50 *
51 * For additional information visit the project home page at
52 * http://www.ethernut.de/
53 */
54
55 #include <common.h>
56 #include <net.h>
57 #include <netdev.h>
58 #include <miiphy.h>
59 #include <i2c.h>
60 #include <mmc.h>
61 #include <atmel_mci.h>
62
63 #include <asm/arch/at91sam9260.h>
64 #include <asm/arch/at91sam9260_matrix.h>
65 #include <asm/arch/at91sam9_smc.h>
66 #include <asm/arch/at91_common.h>
67 #include <asm/arch/clk.h>
68 #include <asm/arch/gpio.h>
69 #include <asm/io.h>
70 #include <asm/gpio.h>
71
72 #include "ethernut5_pwrman.h"
73
74 DECLARE_GLOBAL_DATA_PTR;
75
76 /*
77 * This is called last during early initialization. Most of the basic
78 * hardware interfaces are up and running.
79 *
80 * The SDRAM hardware has been configured by the first stage boot loader.
81 * We only need to announce its size, using u-boot's memory check.
82 */
dram_init(void)83 int dram_init(void)
84 {
85 gd->ram_size = get_ram_size(
86 (void *)CONFIG_SYS_SDRAM_BASE,
87 CONFIG_SYS_SDRAM_SIZE);
88 return 0;
89 }
90
91 #ifdef CONFIG_CMD_NAND
ethernut5_nand_hw_init(void)92 static void ethernut5_nand_hw_init(void)
93 {
94 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
95 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
96 unsigned long csa;
97
98 /* Assign CS3 to NAND/SmartMedia Interface */
99 csa = readl(&matrix->ebicsa);
100 csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
101 writel(csa, &matrix->ebicsa);
102
103 /* Configure SMC CS3 for NAND/SmartMedia */
104 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
105 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
106 &smc->cs[3].setup);
107 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
108 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
109 &smc->cs[3].pulse);
110 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
111 &smc->cs[3].cycle);
112 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
113 AT91_SMC_MODE_EXNW_DISABLE |
114 AT91_SMC_MODE_DBW_8 |
115 AT91_SMC_MODE_TDF_CYCLE(2),
116 &smc->cs[3].mode);
117
118 #ifdef CONFIG_SYS_NAND_READY_PIN
119 /* Ready pin is optional. */
120 at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
121 #endif
122 gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
123 }
124 #endif
125
126 /*
127 * This is called first during late initialization.
128 */
board_init(void)129 int board_init(void)
130 {
131 at91_periph_clk_enable(ATMEL_ID_PIOA);
132 at91_periph_clk_enable(ATMEL_ID_PIOB);
133 at91_periph_clk_enable(ATMEL_ID_PIOC);
134
135 /* Set adress of boot parameters. */
136 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
137 /* Initialize UARTs and power management. */
138 ethernut5_power_init();
139 #ifdef CONFIG_CMD_NAND
140 ethernut5_nand_hw_init();
141 #endif
142 return 0;
143 }
144
145 #ifdef CONFIG_MACB
146 /*
147 * This is optionally called last during late initialization.
148 */
board_eth_init(bd_t * bis)149 int board_eth_init(bd_t *bis)
150 {
151 const char *devname;
152 unsigned short mode;
153
154 at91_periph_clk_enable(ATMEL_ID_EMAC0);
155
156 /* Need to reset PHY via power management. */
157 ethernut5_phy_reset();
158 /* Set peripheral pins. */
159 at91_macb_hw_init();
160 /* Basic EMAC initialization. */
161 if (macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, CONFIG_PHY_ID))
162 return -1;
163 /*
164 * Early board revisions have a pull-down at the PHY's MODE0
165 * strap pin, which forces the PHY into power down. Here we
166 * switch to all-capable mode.
167 */
168 devname = miiphy_get_current_dev();
169 if (miiphy_read(devname, 0, 18, &mode) == 0) {
170 /* Set mode[2:0] to 0b111. */
171 mode |= 0x00E0;
172 miiphy_write(devname, 0, 18, mode);
173 /* Soft reset overrides strap pins. */
174 miiphy_write(devname, 0, MII_BMCR, BMCR_RESET);
175 }
176 /* Sync environment with network devices, needed for nfsroot. */
177 return eth_init();
178 }
179 #endif
180
181 #ifdef CONFIG_GENERIC_ATMEL_MCI
board_mmc_init(bd_t * bd)182 int board_mmc_init(bd_t *bd)
183 {
184 at91_periph_clk_enable(ATMEL_ID_MCI);
185
186 /* Initialize MCI hardware. */
187 at91_mci_hw_init();
188 /* Register the device. */
189 return atmel_mci_init((void *)ATMEL_BASE_MCI);
190 }
191
board_mmc_getcd(struct mmc * mmc)192 int board_mmc_getcd(struct mmc *mmc)
193 {
194 return !at91_get_pio_value(CONFIG_SYS_MMC_CD_PIN);
195 }
196 #endif
197