1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2019 NXP
4 */
5
6 #include <common.h>
7 #include <spl.h>
8 #include <asm/io.h>
9 #include <asm/mach-imx/iomux-v3.h>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/imx8mm_pins.h>
12 #include <asm/arch/sys_proto.h>
13 #include <asm/mach-imx/boot_mode.h>
14 #include <asm/arch/ddr.h>
15
16 #include <dm/uclass.h>
17 #include <dm/device.h>
18 #include <dm/uclass-internal.h>
19 #include <dm/device-internal.h>
20
21 #include <power/pmic.h>
22 #include <power/bd71837.h>
23
24 DECLARE_GLOBAL_DATA_PTR;
25
spl_board_boot_device(enum boot_device boot_dev_spl)26 int spl_board_boot_device(enum boot_device boot_dev_spl)
27 {
28 switch (boot_dev_spl) {
29 case SD2_BOOT:
30 case MMC2_BOOT:
31 return BOOT_DEVICE_MMC1;
32 case SD3_BOOT:
33 case MMC3_BOOT:
34 return BOOT_DEVICE_MMC2;
35 default:
36 return BOOT_DEVICE_NONE;
37 }
38 }
39
spl_dram_init(void)40 void spl_dram_init(void)
41 {
42 ddr_init(&dram_timing);
43 }
44
spl_board_init(void)45 void spl_board_init(void)
46 {
47 puts("Normal Boot\n");
48 }
49
50 #ifdef CONFIG_SPL_LOAD_FIT
board_fit_config_name_match(const char * name)51 int board_fit_config_name_match(const char *name)
52 {
53 /* Just empty function now - can't decide what to choose */
54 debug("%s: %s\n", __func__, name);
55
56 return 0;
57 }
58 #endif
59
60 #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
61 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
62
63 static iomux_v3_cfg_t const uart_pads[] = {
64 IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
65 IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
66 };
67
68 static iomux_v3_cfg_t const wdog_pads[] = {
69 IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
70 };
71
board_early_init_f(void)72 int board_early_init_f(void)
73 {
74 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
75
76 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
77
78 set_wdog_reset(wdog);
79
80 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
81
82 return 0;
83 }
84
power_init_board(void)85 int power_init_board(void)
86 {
87 struct udevice *dev;
88 int ret;
89
90 ret = pmic_get("pmic@4b", &dev);
91 if (ret == -ENODEV) {
92 puts("No pmic\n");
93 return 0;
94 }
95 if (ret != 0)
96 return ret;
97
98 /* decrease RESET key long push time from the default 10s to 10ms */
99 pmic_reg_write(dev, BD718XX_PWRONCONFIG1, 0x0);
100
101 /* unlock the PMIC regs */
102 pmic_reg_write(dev, BD718XX_REGLOCK, 0x1);
103
104 /* increase VDD_SOC to typical value 0.85v before first DRAM access */
105 pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f);
106
107 /* increase VDD_DRAM to 0.975v for 3Ghz DDR */
108 pmic_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83);
109
110 #ifndef CONFIG_IMX8M_LPDDR4
111 /* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */
112 pmic_reg_write(dev, BD718XX_4TH_NODVS_BUCK_VOLT, 0x28);
113 #endif
114
115 /* lock the PMIC regs */
116 pmic_reg_write(dev, BD718XX_REGLOCK, 0x11);
117
118 return 0;
119 }
120
board_init_f(ulong dummy)121 void board_init_f(ulong dummy)
122 {
123 struct udevice *dev;
124 int ret;
125
126 arch_cpu_init();
127
128 init_uart_clk(1);
129
130 board_early_init_f();
131
132 timer_init();
133
134 preloader_console_init();
135
136 /* Clear the BSS. */
137 memset(__bss_start, 0, __bss_end - __bss_start);
138
139 ret = spl_early_init();
140 if (ret) {
141 debug("spl_early_init() failed: %d\n", ret);
142 hang();
143 }
144
145 ret = uclass_get_device_by_name(UCLASS_CLK,
146 "clock-controller@30380000",
147 &dev);
148 if (ret < 0) {
149 printf("Failed to find clock node. Check device tree\n");
150 hang();
151 }
152
153 enable_tzc380();
154
155 power_init_board();
156
157 /* DDR initialization */
158 spl_dram_init();
159
160 board_init_r(NULL, 0);
161 }
162
do_reset(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])163 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
164 {
165 puts ("resetting ...\n");
166
167 reset_cpu(WDOG1_BASE_ADDR);
168
169 return 0;
170 }
171