1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2018 NXP
4 */
5
6 #include <common.h>
7 #include <env.h>
8 #include <init.h>
9 #include <malloc.h>
10 #include <errno.h>
11 #include <asm/io.h>
12 #include <miiphy.h>
13 #include <netdev.h>
14 #include <asm/mach-imx/iomux-v3.h>
15 #include <asm-generic/gpio.h>
16 #include <fsl_esdhc_imx.h>
17 #include <mmc.h>
18 #include <asm/arch/imx8mq_pins.h>
19 #include <asm/arch/sys_proto.h>
20 #include <asm/mach-imx/gpio.h>
21 #include <asm/mach-imx/mxc_i2c.h>
22 #include <asm/arch/clock.h>
23 #include <spl.h>
24 #include <power/pmic.h>
25 #include <power/pfuze100_pmic.h>
26 #include "../common/pfuze.h"
27
28 DECLARE_GLOBAL_DATA_PTR;
29
30 #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
31
32 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
33
34 static iomux_v3_cfg_t const wdog_pads[] = {
35 IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
36 };
37
38 static iomux_v3_cfg_t const uart_pads[] = {
39 IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
40 IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
41 };
42
board_early_init_f(void)43 int board_early_init_f(void)
44 {
45 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
46
47 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
48 set_wdog_reset(wdog);
49
50 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
51
52 return 0;
53 }
54
dram_init(void)55 int dram_init(void)
56 {
57 /* rom_pointer[1] contains the size of TEE occupies */
58 if (rom_pointer[1])
59 gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
60 else
61 gd->ram_size = PHYS_SDRAM_SIZE;
62
63 return 0;
64 }
65
66 #ifdef CONFIG_FEC_MXC
67 #define FEC_RST_PAD IMX_GPIO_NR(1, 9)
68 static iomux_v3_cfg_t const fec1_rst_pads[] = {
69 IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL),
70 };
71
setup_iomux_fec(void)72 static void setup_iomux_fec(void)
73 {
74 imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
75 ARRAY_SIZE(fec1_rst_pads));
76
77 gpio_request(IMX_GPIO_NR(1, 9), "fec1_rst");
78 gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
79 udelay(500);
80 gpio_direction_output(IMX_GPIO_NR(1, 9), 1);
81 }
82
setup_fec(void)83 static int setup_fec(void)
84 {
85 struct iomuxc_gpr_base_regs *gpr =
86 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
87
88 setup_iomux_fec();
89
90 /* Use 125M anatop REF_CLK1 for ENET1, not from external */
91 clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
92 return set_clk_enet(ENET_125MHZ);
93 }
94
board_phy_config(struct phy_device * phydev)95 int board_phy_config(struct phy_device *phydev)
96 {
97 /* enable rgmii rxc skew and phy mode select to RGMII copper */
98 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
99 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
100
101 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
102 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
103
104 if (phydev->drv->config)
105 phydev->drv->config(phydev);
106 return 0;
107 }
108 #endif
109
board_init(void)110 int board_init(void)
111 {
112 #ifdef CONFIG_FEC_MXC
113 setup_fec();
114 #endif
115
116 return 0;
117 }
118
board_mmc_get_env_dev(int devno)119 int board_mmc_get_env_dev(int devno)
120 {
121 return devno;
122 }
123
board_late_init(void)124 int board_late_init(void)
125 {
126 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
127 env_set("board_name", "EVK");
128 env_set("board_rev", "iMX8MQ");
129 #endif
130
131 return 0;
132 }
133