1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2014 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <i2c.h>
8 #include <init.h>
9 #include <asm/io.h>
10 #include <asm/arch/immap_ls102xa.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/fsl_serdes.h>
13 #include <asm/arch/ls102xa_devdis.h>
14 #include <asm/arch/ls102xa_soc.h>
15 #include <hwconfig.h>
16 #include <mmc.h>
17 #include <fsl_csu.h>
18 #include <fsl_ifc.h>
19 #include <fsl_immap.h>
20 #include <netdev.h>
21 #include <fsl_mdio.h>
22 #include <tsec.h>
23 #include <fsl_sec.h>
24 #include <fsl_devdis.h>
25 #include <spl.h>
26 #include "../common/sleep.h"
27 #ifdef CONFIG_U_QE
28 #include <fsl_qe.h>
29 #endif
30 #include <fsl_validate.h>
31
32
33 DECLARE_GLOBAL_DATA_PTR;
34
35 #define VERSION_MASK 0x00FF
36 #define BANK_MASK 0x0001
37 #define CONFIG_RESET 0x1
38 #define INIT_RESET 0x1
39
40 #define CPLD_SET_MUX_SERDES 0x20
41 #define CPLD_SET_BOOT_BANK 0x40
42
43 #define BOOT_FROM_UPPER_BANK 0x0
44 #define BOOT_FROM_LOWER_BANK 0x1
45
46 #define LANEB_SATA (0x01)
47 #define LANEB_SGMII1 (0x02)
48 #define LANEC_SGMII1 (0x04)
49 #define LANEC_PCIEX1 (0x08)
50 #define LANED_PCIEX2 (0x10)
51 #define LANED_SGMII2 (0x20)
52
53 #define MASK_LANE_B 0x1
54 #define MASK_LANE_C 0x2
55 #define MASK_LANE_D 0x4
56 #define MASK_SGMII 0x8
57
58 #define KEEP_STATUS 0x0
59 #define NEED_RESET 0x1
60
61 #define SOFT_MUX_ON_I2C3_IFC 0x2
62 #define SOFT_MUX_ON_CAN3_USB2 0x8
63 #define SOFT_MUX_ON_QE_LCD 0x10
64
65 #define PIN_I2C3_IFC_MUX_I2C3 0x0
66 #define PIN_I2C3_IFC_MUX_IFC 0x1
67 #define PIN_CAN3_USB2_MUX_USB2 0x0
68 #define PIN_CAN3_USB2_MUX_CAN3 0x1
69 #define PIN_QE_LCD_MUX_LCD 0x0
70 #define PIN_QE_LCD_MUX_QE 0x1
71
72 struct cpld_data {
73 u8 cpld_ver; /* cpld revision */
74 u8 cpld_ver_sub; /* cpld sub revision */
75 u8 pcba_ver; /* pcb revision number */
76 u8 system_rst; /* reset system by cpld */
77 u8 soft_mux_on; /* CPLD override physical switches Enable */
78 u8 cfg_rcw_src1; /* Reset config word 1 */
79 u8 cfg_rcw_src2; /* Reset config word 2 */
80 u8 vbank; /* Flash bank selection Control */
81 u8 gpio; /* GPIO for TWR-ELEV */
82 u8 i2c3_ifc_mux;
83 u8 mux_spi2;
84 u8 can3_usb2_mux; /* CAN3 and USB2 Selection */
85 u8 qe_lcd_mux; /* QE and LCD Selection */
86 u8 serdes_mux; /* Multiplexed pins for SerDes Lanes */
87 u8 global_rst; /* reset with init CPLD reg to default */
88 u8 rev1; /* Reserved */
89 u8 rev2; /* Reserved */
90 };
91
92 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
cpld_show(void)93 static void cpld_show(void)
94 {
95 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
96
97 printf("CPLD: V%x.%x\nPCBA: V%x.0\nVBank: %d\n",
98 in_8(&cpld_data->cpld_ver) & VERSION_MASK,
99 in_8(&cpld_data->cpld_ver_sub) & VERSION_MASK,
100 in_8(&cpld_data->pcba_ver) & VERSION_MASK,
101 in_8(&cpld_data->vbank) & BANK_MASK);
102
103 #ifdef CONFIG_DEBUG
104 printf("soft_mux_on =%x\n",
105 in_8(&cpld_data->soft_mux_on));
106 printf("cfg_rcw_src1 =%x\n",
107 in_8(&cpld_data->cfg_rcw_src1));
108 printf("cfg_rcw_src2 =%x\n",
109 in_8(&cpld_data->cfg_rcw_src2));
110 printf("vbank =%x\n",
111 in_8(&cpld_data->vbank));
112 printf("gpio =%x\n",
113 in_8(&cpld_data->gpio));
114 printf("i2c3_ifc_mux =%x\n",
115 in_8(&cpld_data->i2c3_ifc_mux));
116 printf("mux_spi2 =%x\n",
117 in_8(&cpld_data->mux_spi2));
118 printf("can3_usb2_mux =%x\n",
119 in_8(&cpld_data->can3_usb2_mux));
120 printf("qe_lcd_mux =%x\n",
121 in_8(&cpld_data->qe_lcd_mux));
122 printf("serdes_mux =%x\n",
123 in_8(&cpld_data->serdes_mux));
124 #endif
125 }
126 #endif
127
checkboard(void)128 int checkboard(void)
129 {
130 puts("Board: LS1021ATWR\n");
131 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
132 cpld_show();
133 #endif
134
135 return 0;
136 }
137
ddrmc_init(void)138 void ddrmc_init(void)
139 {
140 struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
141 u32 temp_sdram_cfg, tmp;
142
143 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
144
145 out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
146 out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
147
148 out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
149 out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
150 out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
151 out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
152 out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
153 out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
154
155 #ifdef CONFIG_DEEP_SLEEP
156 if (is_warm_boot()) {
157 out_be32(&ddr->sdram_cfg_2,
158 DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT);
159 out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
160 out_be32(&ddr->init_ext_addr, (1 << 31));
161
162 /* DRAM VRef will not be trained */
163 out_be32(&ddr->ddr_cdr2,
164 DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN);
165 } else
166 #endif
167 {
168 out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
169 out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
170 }
171
172 out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
173 out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
174
175 out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
176
177 out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
178
179 out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
180 out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
181
182 out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
183
184 out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
185 out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
186
187 out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
188
189 /* DDR erratum A-009942 */
190 tmp = in_be32(&ddr->debug[28]);
191 out_be32(&ddr->debug[28], tmp | 0x0070006f);
192
193 udelay(1);
194
195 #ifdef CONFIG_DEEP_SLEEP
196 if (is_warm_boot()) {
197 /* enter self-refresh */
198 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
199 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
200 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
201
202 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI);
203 } else
204 #endif
205 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
206
207 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
208
209 #ifdef CONFIG_DEEP_SLEEP
210 if (is_warm_boot()) {
211 /* exit self-refresh */
212 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
213 temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
214 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
215 }
216 #endif
217 }
218
dram_init(void)219 int dram_init(void)
220 {
221 #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
222 ddrmc_init();
223 #endif
224
225 erratum_a008850_post();
226
227 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
228
229 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
230 fsl_dp_resume();
231 #endif
232
233 return 0;
234 }
235
board_eth_init(bd_t * bis)236 int board_eth_init(bd_t *bis)
237 {
238 return pci_eth_init(bis);
239 }
240
241 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
convert_serdes_mux(int type,int need_reset)242 static void convert_serdes_mux(int type, int need_reset)
243 {
244 char current_serdes;
245 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
246
247 current_serdes = cpld_data->serdes_mux;
248
249 switch (type) {
250 case LANEB_SATA:
251 current_serdes &= ~MASK_LANE_B;
252 break;
253 case LANEB_SGMII1:
254 current_serdes |= (MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
255 break;
256 case LANEC_SGMII1:
257 current_serdes &= ~(MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
258 break;
259 case LANED_SGMII2:
260 current_serdes |= MASK_LANE_D;
261 break;
262 case LANEC_PCIEX1:
263 current_serdes |= MASK_LANE_C;
264 break;
265 case (LANED_PCIEX2 | LANEC_PCIEX1):
266 current_serdes |= MASK_LANE_C;
267 current_serdes &= ~MASK_LANE_D;
268 break;
269 default:
270 printf("CPLD serdes MUX: unsupported MUX type 0x%x\n", type);
271 return;
272 }
273
274 cpld_data->soft_mux_on |= CPLD_SET_MUX_SERDES;
275 cpld_data->serdes_mux = current_serdes;
276
277 if (need_reset == 1) {
278 printf("Reset board to enable configuration\n");
279 cpld_data->system_rst = CONFIG_RESET;
280 }
281 }
282
config_serdes_mux(void)283 int config_serdes_mux(void)
284 {
285 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
286 u32 protocol = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
287
288 protocol >>= RCWSR4_SRDS1_PRTCL_SHIFT;
289 switch (protocol) {
290 case 0x10:
291 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
292 convert_serdes_mux(LANED_PCIEX2 |
293 LANEC_PCIEX1, KEEP_STATUS);
294 break;
295 case 0x20:
296 convert_serdes_mux(LANEB_SGMII1, KEEP_STATUS);
297 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
298 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
299 break;
300 case 0x30:
301 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
302 convert_serdes_mux(LANEC_SGMII1, KEEP_STATUS);
303 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
304 break;
305 case 0x70:
306 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
307 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
308 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
309 break;
310 }
311
312 return 0;
313 }
314 #endif
315
316 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
config_board_mux(void)317 int config_board_mux(void)
318 {
319 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
320 int conflict_flag;
321
322 conflict_flag = 0;
323 if (hwconfig("i2c3")) {
324 conflict_flag++;
325 cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
326 cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_I2C3;
327 }
328
329 if (hwconfig("ifc")) {
330 conflict_flag++;
331 /* some signals can not enable simultaneous*/
332 if (conflict_flag > 1)
333 goto conflict;
334 cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
335 cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_IFC;
336 }
337
338 conflict_flag = 0;
339 if (hwconfig("usb2")) {
340 conflict_flag++;
341 cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
342 cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_USB2;
343 }
344
345 if (hwconfig("can3")) {
346 conflict_flag++;
347 /* some signals can not enable simultaneous*/
348 if (conflict_flag > 1)
349 goto conflict;
350 cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
351 cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_CAN3;
352 }
353
354 conflict_flag = 0;
355 if (hwconfig("lcd")) {
356 conflict_flag++;
357 cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
358 cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_LCD;
359 }
360
361 if (hwconfig("qe")) {
362 conflict_flag++;
363 /* some signals can not enable simultaneous*/
364 if (conflict_flag > 1)
365 goto conflict;
366 cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
367 cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_QE;
368 }
369
370 return 0;
371
372 conflict:
373 printf("WARNING: pin conflict! MUX setting may failed!\n");
374 return 0;
375 }
376 #endif
377
board_early_init_f(void)378 int board_early_init_f(void)
379 {
380 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
381
382 #ifdef CONFIG_TSEC_ENET
383 /* clear BD & FR bits for BE BD's and frame data */
384 clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
385 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
386 #endif
387
388 #ifdef CONFIG_FSL_IFC
389 init_early_memctl_regs();
390 #endif
391
392 arch_soc_init();
393
394 #if defined(CONFIG_DEEP_SLEEP)
395 if (is_warm_boot()) {
396 timer_init();
397 dram_init();
398 }
399 #endif
400
401 return 0;
402 }
403
404 #ifdef CONFIG_SPL_BUILD
board_init_f(ulong dummy)405 void board_init_f(ulong dummy)
406 {
407 void (*second_uboot)(void);
408
409 /* Clear the BSS */
410 memset(__bss_start, 0, __bss_end - __bss_start);
411
412 get_clocks();
413
414 #if defined(CONFIG_DEEP_SLEEP)
415 if (is_warm_boot())
416 fsl_dp_disable_console();
417 #endif
418
419 preloader_console_init();
420
421 timer_init();
422 dram_init();
423
424 /* Allow OCRAM access permission as R/W */
425 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
426 enable_layerscape_ns_access();
427 #endif
428
429 /*
430 * if it is woken up from deep sleep, then jump to second
431 * stage uboot and continue executing without recopying
432 * it from SD since it has already been reserved in memeory
433 * in last boot.
434 */
435 if (is_warm_boot()) {
436 second_uboot = (void (*)(void))CONFIG_SYS_TEXT_BASE;
437 second_uboot();
438 }
439
440 board_init_r(NULL, 0);
441 }
442 #endif
443
444 #ifdef CONFIG_DEEP_SLEEP
445 /* program the regulator (MC34VR500) to support deep sleep */
ls1twr_program_regulator(void)446 void ls1twr_program_regulator(void)
447 {
448 unsigned int i2c_bus;
449 u8 i2c_device_id;
450
451 #define LS1TWR_I2C_BUS_MC34VR500 1
452 #define MC34VR500_ADDR 0x8
453 #define MC34VR500_DEVICEID 0x4
454 #define MC34VR500_DEVICEID_MASK 0x0f
455
456 i2c_bus = i2c_get_bus_num();
457 i2c_set_bus_num(LS1TWR_I2C_BUS_MC34VR500);
458 i2c_device_id = i2c_reg_read(MC34VR500_ADDR, 0x0) &
459 MC34VR500_DEVICEID_MASK;
460 if (i2c_device_id != MC34VR500_DEVICEID) {
461 printf("The regulator (MC34VR500) does not exist. The device does not support deep sleep.\n");
462 return;
463 }
464
465 i2c_reg_write(MC34VR500_ADDR, 0x31, 0x4);
466 i2c_reg_write(MC34VR500_ADDR, 0x4d, 0x4);
467 i2c_reg_write(MC34VR500_ADDR, 0x6d, 0x38);
468 i2c_reg_write(MC34VR500_ADDR, 0x6f, 0x37);
469 i2c_reg_write(MC34VR500_ADDR, 0x71, 0x30);
470
471 i2c_set_bus_num(i2c_bus);
472 }
473 #endif
474
board_init(void)475 int board_init(void)
476 {
477 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
478 erratum_a010315();
479 #endif
480
481 #ifndef CONFIG_SYS_FSL_NO_SERDES
482 fsl_serdes_init();
483 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
484 config_serdes_mux();
485 #endif
486 #endif
487
488 ls102xa_smmu_stream_id_init();
489
490 #ifdef CONFIG_U_QE
491 u_qe_init();
492 #endif
493
494 #ifdef CONFIG_DEEP_SLEEP
495 ls1twr_program_regulator();
496 #endif
497 return 0;
498 }
499
500 #if defined(CONFIG_SPL_BUILD)
spl_board_init(void)501 void spl_board_init(void)
502 {
503 ls102xa_smmu_stream_id_init();
504 }
505 #endif
506
507 #ifdef CONFIG_BOARD_LATE_INIT
board_late_init(void)508 int board_late_init(void)
509 {
510 #ifdef CONFIG_CHAIN_OF_TRUST
511 fsl_setenv_chain_of_trust();
512 #endif
513
514 return 0;
515 }
516 #endif
517
518 #if defined(CONFIG_MISC_INIT_R)
misc_init_r(void)519 int misc_init_r(void)
520 {
521 #ifdef CONFIG_FSL_DEVICE_DISABLE
522 device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
523 #endif
524 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
525 config_board_mux();
526 #endif
527
528 #ifdef CONFIG_FSL_CAAM
529 return sec_init();
530 #endif
531 }
532 #endif
533
534 #if defined(CONFIG_DEEP_SLEEP)
board_sleep_prepare(void)535 void board_sleep_prepare(void)
536 {
537 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
538 enable_layerscape_ns_access();
539 #endif
540 }
541 #endif
542
ft_board_setup(void * blob,bd_t * bd)543 int ft_board_setup(void *blob, bd_t *bd)
544 {
545 ft_cpu_setup(blob, bd);
546
547 #ifdef CONFIG_PCI
548 ft_pci_setup(blob, bd);
549 #endif
550
551 return 0;
552 }
553
flash_read8(void * addr)554 u8 flash_read8(void *addr)
555 {
556 return __raw_readb(addr + 1);
557 }
558
flash_write16(u16 val,void * addr)559 void flash_write16(u16 val, void *addr)
560 {
561 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
562
563 __raw_writew(shftval, addr);
564 }
565
flash_read16(void * addr)566 u16 flash_read16(void *addr)
567 {
568 u16 val = __raw_readw(addr);
569
570 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
571 }
572
573 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) \
574 && !defined(CONFIG_SPL_BUILD)
convert_flash_bank(char bank)575 static void convert_flash_bank(char bank)
576 {
577 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
578
579 printf("Now switch to boot from flash bank %d.\n", bank);
580 cpld_data->soft_mux_on = CPLD_SET_BOOT_BANK;
581 cpld_data->vbank = bank;
582
583 printf("Reset board to enable configuration.\n");
584 cpld_data->system_rst = CONFIG_RESET;
585 }
586
flash_bank_cmd(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])587 static int flash_bank_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
588 char * const argv[])
589 {
590 if (argc != 2)
591 return CMD_RET_USAGE;
592 if (strcmp(argv[1], "0") == 0)
593 convert_flash_bank(BOOT_FROM_UPPER_BANK);
594 else if (strcmp(argv[1], "1") == 0)
595 convert_flash_bank(BOOT_FROM_LOWER_BANK);
596 else
597 return CMD_RET_USAGE;
598
599 return 0;
600 }
601
602 U_BOOT_CMD(
603 boot_bank, 2, 0, flash_bank_cmd,
604 "Flash bank Selection Control",
605 "bank[0-upper bank/1-lower bank] (e.g. boot_bank 0)"
606 );
607
cpld_reset_cmd(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])608 static int cpld_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
609 char * const argv[])
610 {
611 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
612
613 if (argc > 2)
614 return CMD_RET_USAGE;
615 if ((argc == 1) || (strcmp(argv[1], "conf") == 0))
616 cpld_data->system_rst = CONFIG_RESET;
617 else if (strcmp(argv[1], "init") == 0)
618 cpld_data->global_rst = INIT_RESET;
619 else
620 return CMD_RET_USAGE;
621
622 return 0;
623 }
624
625 U_BOOT_CMD(
626 cpld_reset, 2, 0, cpld_reset_cmd,
627 "Reset via CPLD",
628 "conf\n"
629 " -reset with current CPLD configuration\n"
630 "init\n"
631 " -reset and initial CPLD configuration with default value"
632
633 );
634
print_serdes_mux(void)635 static void print_serdes_mux(void)
636 {
637 char current_serdes;
638 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
639
640 current_serdes = cpld_data->serdes_mux;
641
642 printf("Serdes Lane B: ");
643 if ((current_serdes & MASK_LANE_B) == 0)
644 printf("SATA,\n");
645 else
646 printf("SGMII 1,\n");
647
648 printf("Serdes Lane C: ");
649 if ((current_serdes & MASK_LANE_C) == 0)
650 printf("SGMII 1,\n");
651 else
652 printf("PCIe,\n");
653
654 printf("Serdes Lane D: ");
655 if ((current_serdes & MASK_LANE_D) == 0)
656 printf("PCIe,\n");
657 else
658 printf("SGMII 2,\n");
659
660 printf("SGMII 1 is on lane ");
661 if ((current_serdes & MASK_SGMII) == 0)
662 printf("C.\n");
663 else
664 printf("B.\n");
665 }
666
serdes_mux_cmd(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])667 static int serdes_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
668 char * const argv[])
669 {
670 if (argc != 2)
671 return CMD_RET_USAGE;
672 if (strcmp(argv[1], "sata") == 0) {
673 printf("Set serdes lane B to SATA.\n");
674 convert_serdes_mux(LANEB_SATA, NEED_RESET);
675 } else if (strcmp(argv[1], "sgmii1b") == 0) {
676 printf("Set serdes lane B to SGMII 1.\n");
677 convert_serdes_mux(LANEB_SGMII1, NEED_RESET);
678 } else if (strcmp(argv[1], "sgmii1c") == 0) {
679 printf("Set serdes lane C to SGMII 1.\n");
680 convert_serdes_mux(LANEC_SGMII1, NEED_RESET);
681 } else if (strcmp(argv[1], "sgmii2") == 0) {
682 printf("Set serdes lane D to SGMII 2.\n");
683 convert_serdes_mux(LANED_SGMII2, NEED_RESET);
684 } else if (strcmp(argv[1], "pciex1") == 0) {
685 printf("Set serdes lane C to PCIe X1.\n");
686 convert_serdes_mux(LANEC_PCIEX1, NEED_RESET);
687 } else if (strcmp(argv[1], "pciex2") == 0) {
688 printf("Set serdes lane C & lane D to PCIe X2.\n");
689 convert_serdes_mux((LANED_PCIEX2 | LANEC_PCIEX1), NEED_RESET);
690 } else if (strcmp(argv[1], "show") == 0) {
691 print_serdes_mux();
692 } else {
693 return CMD_RET_USAGE;
694 }
695
696 return 0;
697 }
698
699 U_BOOT_CMD(
700 lane_bank, 2, 0, serdes_mux_cmd,
701 "Multiplexed function setting for SerDes Lanes",
702 "sata\n"
703 " -change lane B to sata\n"
704 "lane_bank sgmii1b\n"
705 " -change lane B to SGMII1\n"
706 "lane_bank sgmii1c\n"
707 " -change lane C to SGMII1\n"
708 "lane_bank sgmii2\n"
709 " -change lane D to SGMII2\n"
710 "lane_bank pciex1\n"
711 " -change lane C to PCIeX1\n"
712 "lane_bank pciex2\n"
713 " -change lane C & lane D to PCIeX2\n"
714 "\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n"
715 );
716 #endif
717