1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2015 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <env.h>
8 #include <netdev.h>
9 #include <asm/io.h>
10 #include <asm/arch/fsl_serdes.h>
11 #include <hwconfig.h>
12 #include <fsl_mdio.h>
13 #include <malloc.h>
14 #include <fm_eth.h>
15 #include <i2c.h>
16 #include <miiphy.h>
17 #include <fsl-mc/fsl_mc.h>
18 #include <fsl-mc/ldpaa_wriop.h>
19
20 #include "../common/qixis.h"
21
22 #include "ls2080aqds_qixis.h"
23
24 #define MC_BOOT_ENV_VAR "mcinitcmd"
25
26 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
27 /* - In LS2080A there are only 16 SERDES lanes, spread across 2 SERDES banks.
28 * Bank 1 -> Lanes A, B, C, D, E, F, G, H
29 * Bank 2 -> Lanes A,B, C, D, E, F, G, H
30 */
31
32 /* Mapping of 16 SERDES lanes to LS2080A QDS board slots. A value of '0' here
33 * means that the mapping must be determined dynamically, or that the lane
34 * maps to something other than a board slot.
35 */
36
37 static u8 lane_to_slot_fsm1[] = {
38 0, 0, 0, 0, 0, 0, 0, 0
39 };
40
41 static u8 lane_to_slot_fsm2[] = {
42 0, 0, 0, 0, 0, 0, 0, 0
43 };
44
45 /* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs
46 * housed.
47 */
48
49 static int xqsgii_riser_phy_addr[] = {
50 XQSGMII_CARD_PHY1_PORT0_ADDR,
51 XQSGMII_CARD_PHY2_PORT0_ADDR,
52 XQSGMII_CARD_PHY3_PORT0_ADDR,
53 XQSGMII_CARD_PHY4_PORT0_ADDR,
54 XQSGMII_CARD_PHY3_PORT2_ADDR,
55 XQSGMII_CARD_PHY1_PORT2_ADDR,
56 XQSGMII_CARD_PHY4_PORT2_ADDR,
57 XQSGMII_CARD_PHY2_PORT2_ADDR,
58 };
59
60 static int sgmii_riser_phy_addr[] = {
61 SGMII_CARD_PORT1_PHY_ADDR,
62 SGMII_CARD_PORT2_PHY_ADDR,
63 SGMII_CARD_PORT3_PHY_ADDR,
64 SGMII_CARD_PORT4_PHY_ADDR,
65 };
66
67 /* Slot2 does not have EMI connections */
68 #define EMI_NONE 0xFF
69 #define EMI1_SLOT1 0
70 #define EMI1_SLOT2 1
71 #define EMI1_SLOT3 2
72 #define EMI1_SLOT4 3
73 #define EMI1_SLOT5 4
74 #define EMI1_SLOT6 5
75 #define EMI2 6
76 #define SFP_TX 0
77
78 static const char * const mdio_names[] = {
79 "LS2080A_QDS_MDIO0",
80 "LS2080A_QDS_MDIO1",
81 "LS2080A_QDS_MDIO2",
82 "LS2080A_QDS_MDIO3",
83 "LS2080A_QDS_MDIO4",
84 "LS2080A_QDS_MDIO5",
85 DEFAULT_WRIOP_MDIO2_NAME,
86 };
87
88 struct ls2080a_qds_mdio {
89 u8 muxval;
90 struct mii_dev *realbus;
91 };
92
93 struct reg_pair {
94 uint addr;
95 u8 *val;
96 };
97
sgmii_configure_repeater(int serdes_port)98 static void sgmii_configure_repeater(int serdes_port)
99 {
100 struct mii_dev *bus;
101 uint8_t a = 0xf;
102 int i, j, k, ret;
103 int dpmac_id = 0, dpmac, mii_bus = 0;
104 unsigned short value;
105 char dev[2][20] = {"LS2080A_QDS_MDIO0", "LS2080A_QDS_MDIO3"};
106 uint8_t i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5f, 0x60};
107
108 uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
109 uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
110 uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
111 uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
112
113 u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20};
114 struct reg_pair reg_pair[10] = {
115 {6, ®_val[0]}, {4, ®_val[1]},
116 {8, ®_val[2]}, {0xf, NULL},
117 {0x11, NULL}, {0x16, NULL},
118 {0x18, NULL}, {0x23, ®_val[3]},
119 {0x2d, ®_val[4]}, {4, ®_val[5]},
120 };
121
122 int *riser_phy_addr = &xqsgii_riser_phy_addr[0];
123 #ifdef CONFIG_DM_I2C
124 struct udevice *udev;
125 #endif
126
127 /* Set I2c to Slot 1 */
128 #ifndef CONFIG_DM_I2C
129 ret = i2c_write(0x77, 0, 0, &a, 1);
130 #else
131 ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev);
132 if (!ret)
133 ret = dm_i2c_write(udev, 0, &a, 1);
134 #endif
135 if (ret)
136 goto error;
137
138 for (dpmac = 0; dpmac < 8; dpmac++) {
139 /* Check the PHY status */
140 switch (serdes_port) {
141 case 1:
142 mii_bus = 0;
143 dpmac_id = dpmac + 1;
144 break;
145 case 2:
146 mii_bus = 1;
147 dpmac_id = dpmac + 9;
148 a = 0xb;
149 #ifndef CONFIG_DM_I2C
150 ret = i2c_write(0x76, 0, 0, &a, 1);
151 #else
152 ret = i2c_get_chip_for_busnum(0, 0x76, 1, &udev);
153 if (!ret)
154 ret = dm_i2c_write(udev, 0, &a, 1);
155 #endif
156 if (ret)
157 goto error;
158 break;
159 }
160
161 ret = miiphy_set_current_dev(dev[mii_bus]);
162 if (ret > 0)
163 goto error;
164
165 bus = mdio_get_current_dev();
166 debug("Reading from bus %s\n", bus->name);
167
168 ret = miiphy_write(dev[mii_bus], riser_phy_addr[dpmac], 0x1f,
169 3);
170 if (ret > 0)
171 goto error;
172
173 mdelay(10);
174 ret = miiphy_read(dev[mii_bus], riser_phy_addr[dpmac], 0x11,
175 &value);
176 if (ret > 0)
177 goto error;
178
179 mdelay(10);
180
181 if ((value & 0xfff) == 0x401) {
182 printf("DPMAC %d:PHY is ..... Configured\n", dpmac_id);
183 miiphy_write(dev[mii_bus], riser_phy_addr[dpmac],
184 0x1f, 0);
185 continue;
186 }
187
188 for (i = 0; i < 4; i++) {
189 for (j = 0; j < 4; j++) {
190 reg_pair[3].val = &ch_a_eq[i];
191 reg_pair[4].val = &ch_a_ctl2[j];
192 reg_pair[5].val = &ch_b_eq[i];
193 reg_pair[6].val = &ch_b_ctl2[j];
194
195 for (k = 0; k < 10; k++) {
196 #ifndef CONFIG_DM_I2C
197 ret = i2c_write(i2c_addr[dpmac],
198 reg_pair[k].addr,
199 1, reg_pair[k].val, 1);
200 #else
201 ret = i2c_get_chip_for_busnum(0,
202 i2c_addr[dpmac],
203 1, &udev);
204 if (!ret)
205 ret = dm_i2c_write(udev,
206 reg_pair[k].addr,
207 reg_pair[k].val, 1);
208 #endif
209 if (ret)
210 goto error;
211 }
212
213 mdelay(100);
214 ret = miiphy_read(dev[mii_bus],
215 riser_phy_addr[dpmac],
216 0x11, &value);
217 if (ret > 0)
218 goto error;
219
220 mdelay(100);
221 ret = miiphy_read(dev[mii_bus],
222 riser_phy_addr[dpmac],
223 0x11, &value);
224 if (ret > 0)
225 goto error;
226
227 if ((value & 0xfff) == 0x401) {
228 printf("DPMAC %d :PHY is configured ",
229 dpmac_id);
230 printf("after setting repeater 0x%x\n",
231 value);
232 i = 5;
233 j = 5;
234 } else {
235 printf("DPMAC %d :PHY is failed to ",
236 dpmac_id);
237 printf("configure the repeater 0x%x\n",
238 value);
239 }
240 }
241 }
242 miiphy_write(dev[mii_bus], riser_phy_addr[dpmac], 0x1f, 0);
243 }
244 error:
245 if (ret)
246 printf("DPMAC %d ..... FAILED to configure PHY\n", dpmac_id);
247 return;
248 }
249
qsgmii_configure_repeater(int dpmac)250 static void qsgmii_configure_repeater(int dpmac)
251 {
252 uint8_t a = 0xf;
253 int i, j, k;
254 int i2c_phy_addr = 0;
255 int phy_addr = 0;
256 int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
257
258 uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
259 uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
260 uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
261 uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
262
263 u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20};
264 struct reg_pair reg_pair[10] = {
265 {6, ®_val[0]}, {4, ®_val[1]},
266 {8, ®_val[2]}, {0xf, NULL},
267 {0x11, NULL}, {0x16, NULL},
268 {0x18, NULL}, {0x23, ®_val[3]},
269 {0x2d, ®_val[4]}, {4, ®_val[5]},
270 };
271
272 const char *dev = "LS2080A_QDS_MDIO0";
273 int ret = 0;
274 unsigned short value;
275 #ifdef CONFIG_DM_I2C
276 struct udevice *udev;
277 #endif
278
279 /* Set I2c to Slot 1 */
280 #ifndef CONFIG_DM_I2C
281 ret = i2c_write(0x77, 0, 0, &a, 1);
282 #else
283 ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev);
284 if (!ret)
285 ret = dm_i2c_write(udev, 0, &a, 1);
286 #endif
287 if (ret)
288 goto error;
289
290 switch (dpmac) {
291 case 1:
292 case 2:
293 case 3:
294 case 4:
295 i2c_phy_addr = i2c_addr[0];
296 phy_addr = 0;
297 break;
298
299 case 5:
300 case 6:
301 case 7:
302 case 8:
303 i2c_phy_addr = i2c_addr[1];
304 phy_addr = 4;
305 break;
306
307 case 9:
308 case 10:
309 case 11:
310 case 12:
311 i2c_phy_addr = i2c_addr[2];
312 phy_addr = 8;
313 break;
314
315 case 13:
316 case 14:
317 case 15:
318 case 16:
319 i2c_phy_addr = i2c_addr[3];
320 phy_addr = 0xc;
321 break;
322 }
323
324 /* Check the PHY status */
325 ret = miiphy_set_current_dev(dev);
326 ret = miiphy_write(dev, phy_addr, 0x1f, 3);
327 mdelay(10);
328 ret = miiphy_read(dev, phy_addr, 0x11, &value);
329 mdelay(10);
330 ret = miiphy_read(dev, phy_addr, 0x11, &value);
331 mdelay(10);
332 if ((value & 0xf) == 0xf) {
333 printf("DPMAC %d :PHY is ..... Configured\n", dpmac);
334 return;
335 }
336
337 for (i = 0; i < 4; i++) {
338 for (j = 0; j < 4; j++) {
339 reg_pair[3].val = &ch_a_eq[i];
340 reg_pair[4].val = &ch_a_ctl2[j];
341 reg_pair[5].val = &ch_b_eq[i];
342 reg_pair[6].val = &ch_b_ctl2[j];
343
344 for (k = 0; k < 10; k++) {
345 #ifndef CONFIG_DM_I2C
346 ret = i2c_write(i2c_phy_addr,
347 reg_pair[k].addr,
348 1, reg_pair[k].val, 1);
349 #else
350 ret = i2c_get_chip_for_busnum(0,
351 i2c_phy_addr,
352 1, &udev);
353 if (!ret)
354 ret = dm_i2c_write(udev,
355 reg_pair[k].addr,
356 reg_pair[k].val, 1);
357 #endif
358 if (ret)
359 goto error;
360 }
361
362 mdelay(100);
363 ret = miiphy_read(dev, phy_addr, 0x11, &value);
364 if (ret > 0)
365 goto error;
366 mdelay(1);
367 ret = miiphy_read(dev, phy_addr, 0x11, &value);
368 if (ret > 0)
369 goto error;
370 mdelay(10);
371 if ((value & 0xf) == 0xf) {
372 printf("DPMAC %d :PHY is ..... Configured\n",
373 dpmac);
374 return;
375 }
376 }
377 }
378 error:
379 printf("DPMAC %d :PHY ..... FAILED to configure PHY\n", dpmac);
380 return;
381 }
382
ls2080a_qds_mdio_name_for_muxval(u8 muxval)383 static const char *ls2080a_qds_mdio_name_for_muxval(u8 muxval)
384 {
385 return mdio_names[muxval];
386 }
387
mii_dev_for_muxval(u8 muxval)388 struct mii_dev *mii_dev_for_muxval(u8 muxval)
389 {
390 struct mii_dev *bus;
391 const char *name = ls2080a_qds_mdio_name_for_muxval(muxval);
392
393 if (!name) {
394 printf("No bus for muxval %x\n", muxval);
395 return NULL;
396 }
397
398 bus = miiphy_get_dev_by_name(name);
399
400 if (!bus) {
401 printf("No bus by name %s\n", name);
402 return NULL;
403 }
404
405 return bus;
406 }
407
ls2080a_qds_enable_SFP_TX(u8 muxval)408 static void ls2080a_qds_enable_SFP_TX(u8 muxval)
409 {
410 u8 brdcfg9;
411
412 brdcfg9 = QIXIS_READ(brdcfg[9]);
413 brdcfg9 &= ~BRDCFG9_SFPTX_MASK;
414 brdcfg9 |= (muxval << BRDCFG9_SFPTX_SHIFT);
415 QIXIS_WRITE(brdcfg[9], brdcfg9);
416 }
417
ls2080a_qds_mux_mdio(u8 muxval)418 static void ls2080a_qds_mux_mdio(u8 muxval)
419 {
420 u8 brdcfg4;
421
422 if (muxval <= 5) {
423 brdcfg4 = QIXIS_READ(brdcfg[4]);
424 brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
425 brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
426 QIXIS_WRITE(brdcfg[4], brdcfg4);
427 }
428 }
429
ls2080a_qds_mdio_read(struct mii_dev * bus,int addr,int devad,int regnum)430 static int ls2080a_qds_mdio_read(struct mii_dev *bus, int addr,
431 int devad, int regnum)
432 {
433 struct ls2080a_qds_mdio *priv = bus->priv;
434
435 ls2080a_qds_mux_mdio(priv->muxval);
436
437 return priv->realbus->read(priv->realbus, addr, devad, regnum);
438 }
439
ls2080a_qds_mdio_write(struct mii_dev * bus,int addr,int devad,int regnum,u16 value)440 static int ls2080a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
441 int regnum, u16 value)
442 {
443 struct ls2080a_qds_mdio *priv = bus->priv;
444
445 ls2080a_qds_mux_mdio(priv->muxval);
446
447 return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
448 }
449
ls2080a_qds_mdio_reset(struct mii_dev * bus)450 static int ls2080a_qds_mdio_reset(struct mii_dev *bus)
451 {
452 struct ls2080a_qds_mdio *priv = bus->priv;
453
454 return priv->realbus->reset(priv->realbus);
455 }
456
ls2080a_qds_mdio_init(char * realbusname,u8 muxval)457 static int ls2080a_qds_mdio_init(char *realbusname, u8 muxval)
458 {
459 struct ls2080a_qds_mdio *pmdio;
460 struct mii_dev *bus = mdio_alloc();
461
462 if (!bus) {
463 printf("Failed to allocate ls2080a_qds MDIO bus\n");
464 return -1;
465 }
466
467 pmdio = malloc(sizeof(*pmdio));
468 if (!pmdio) {
469 printf("Failed to allocate ls2080a_qds private data\n");
470 free(bus);
471 return -1;
472 }
473
474 bus->read = ls2080a_qds_mdio_read;
475 bus->write = ls2080a_qds_mdio_write;
476 bus->reset = ls2080a_qds_mdio_reset;
477 strcpy(bus->name, ls2080a_qds_mdio_name_for_muxval(muxval));
478
479 pmdio->realbus = miiphy_get_dev_by_name(realbusname);
480
481 if (!pmdio->realbus) {
482 printf("No bus with name %s\n", realbusname);
483 free(bus);
484 free(pmdio);
485 return -1;
486 }
487
488 pmdio->muxval = muxval;
489 bus->priv = pmdio;
490
491 return mdio_register(bus);
492 }
493
494 /*
495 * Initialize the dpmac_info array.
496 *
497 */
initialize_dpmac_to_slot(void)498 static void initialize_dpmac_to_slot(void)
499 {
500 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
501 int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
502 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
503 >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
504 int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
505 FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
506 >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
507
508 char *env_hwconfig;
509 env_hwconfig = env_get("hwconfig");
510
511 switch (serdes1_prtcl) {
512 case 0x07:
513 case 0x09:
514 case 0x33:
515 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
516 serdes1_prtcl);
517 lane_to_slot_fsm1[0] = EMI1_SLOT1;
518 lane_to_slot_fsm1[1] = EMI1_SLOT1;
519 lane_to_slot_fsm1[2] = EMI1_SLOT1;
520 lane_to_slot_fsm1[3] = EMI1_SLOT1;
521 if (hwconfig_f("xqsgmii", env_hwconfig)) {
522 lane_to_slot_fsm1[4] = EMI1_SLOT1;
523 lane_to_slot_fsm1[5] = EMI1_SLOT1;
524 lane_to_slot_fsm1[6] = EMI1_SLOT1;
525 lane_to_slot_fsm1[7] = EMI1_SLOT1;
526 } else {
527 lane_to_slot_fsm1[4] = EMI1_SLOT2;
528 lane_to_slot_fsm1[5] = EMI1_SLOT2;
529 lane_to_slot_fsm1[6] = EMI1_SLOT2;
530 lane_to_slot_fsm1[7] = EMI1_SLOT2;
531 }
532 break;
533
534 case 0x39:
535 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
536 serdes1_prtcl);
537 if (hwconfig_f("xqsgmii", env_hwconfig)) {
538 lane_to_slot_fsm1[0] = EMI1_SLOT3;
539 lane_to_slot_fsm1[1] = EMI1_SLOT3;
540 lane_to_slot_fsm1[2] = EMI1_SLOT3;
541 lane_to_slot_fsm1[3] = EMI_NONE;
542 } else {
543 lane_to_slot_fsm1[0] = EMI_NONE;
544 lane_to_slot_fsm1[1] = EMI_NONE;
545 lane_to_slot_fsm1[2] = EMI_NONE;
546 lane_to_slot_fsm1[3] = EMI_NONE;
547 }
548 lane_to_slot_fsm1[4] = EMI1_SLOT3;
549 lane_to_slot_fsm1[5] = EMI1_SLOT3;
550 lane_to_slot_fsm1[6] = EMI1_SLOT3;
551 lane_to_slot_fsm1[7] = EMI_NONE;
552 break;
553
554 case 0x4D:
555 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
556 serdes1_prtcl);
557 if (hwconfig_f("xqsgmii", env_hwconfig)) {
558 lane_to_slot_fsm1[0] = EMI1_SLOT3;
559 lane_to_slot_fsm1[1] = EMI1_SLOT3;
560 lane_to_slot_fsm1[2] = EMI_NONE;
561 lane_to_slot_fsm1[3] = EMI_NONE;
562 } else {
563 lane_to_slot_fsm1[0] = EMI_NONE;
564 lane_to_slot_fsm1[1] = EMI_NONE;
565 lane_to_slot_fsm1[2] = EMI_NONE;
566 lane_to_slot_fsm1[3] = EMI_NONE;
567 }
568 lane_to_slot_fsm1[4] = EMI1_SLOT3;
569 lane_to_slot_fsm1[5] = EMI1_SLOT3;
570 lane_to_slot_fsm1[6] = EMI_NONE;
571 lane_to_slot_fsm1[7] = EMI_NONE;
572 break;
573
574 case 0x2A:
575 case 0x4B:
576 case 0x4C:
577 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
578 serdes1_prtcl);
579 break;
580 default:
581 printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
582 __func__, serdes1_prtcl);
583 break;
584 }
585
586 switch (serdes2_prtcl) {
587 case 0x07:
588 case 0x08:
589 case 0x09:
590 case 0x49:
591 printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n",
592 serdes2_prtcl);
593 lane_to_slot_fsm2[0] = EMI1_SLOT4;
594 lane_to_slot_fsm2[1] = EMI1_SLOT4;
595 lane_to_slot_fsm2[2] = EMI1_SLOT4;
596 lane_to_slot_fsm2[3] = EMI1_SLOT4;
597
598 if (hwconfig_f("xqsgmii", env_hwconfig)) {
599 lane_to_slot_fsm2[4] = EMI1_SLOT4;
600 lane_to_slot_fsm2[5] = EMI1_SLOT4;
601 lane_to_slot_fsm2[6] = EMI1_SLOT4;
602 lane_to_slot_fsm2[7] = EMI1_SLOT4;
603 } else {
604 /* No MDIO physical connection */
605 lane_to_slot_fsm2[4] = EMI1_SLOT6;
606 lane_to_slot_fsm2[5] = EMI1_SLOT6;
607 lane_to_slot_fsm2[6] = EMI1_SLOT6;
608 lane_to_slot_fsm2[7] = EMI1_SLOT6;
609 }
610 break;
611
612 case 0x47:
613 printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n",
614 serdes2_prtcl);
615 lane_to_slot_fsm2[0] = EMI_NONE;
616 lane_to_slot_fsm2[1] = EMI1_SLOT5;
617 lane_to_slot_fsm2[2] = EMI1_SLOT5;
618 lane_to_slot_fsm2[3] = EMI1_SLOT5;
619
620 if (hwconfig_f("xqsgmii", env_hwconfig)) {
621 lane_to_slot_fsm2[4] = EMI_NONE;
622 lane_to_slot_fsm2[5] = EMI1_SLOT5;
623 lane_to_slot_fsm2[6] = EMI1_SLOT5;
624 lane_to_slot_fsm2[7] = EMI1_SLOT5;
625 }
626 break;
627
628 case 0x57:
629 printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n",
630 serdes2_prtcl);
631 if (hwconfig_f("xqsgmii", env_hwconfig)) {
632 lane_to_slot_fsm2[0] = EMI_NONE;
633 lane_to_slot_fsm2[1] = EMI_NONE;
634 lane_to_slot_fsm2[2] = EMI_NONE;
635 lane_to_slot_fsm2[3] = EMI_NONE;
636 }
637 lane_to_slot_fsm2[4] = EMI_NONE;
638 lane_to_slot_fsm2[5] = EMI_NONE;
639 lane_to_slot_fsm2[6] = EMI1_SLOT5;
640 lane_to_slot_fsm2[7] = EMI1_SLOT5;
641 break;
642
643 default:
644 printf(" %s qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n",
645 __func__ , serdes2_prtcl);
646 break;
647 }
648 }
649
ls2080a_handle_phy_interface_sgmii(int dpmac_id)650 void ls2080a_handle_phy_interface_sgmii(int dpmac_id)
651 {
652 int lane, slot;
653 struct mii_dev *bus;
654 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
655 int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
656 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
657 >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
658 int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
659 FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
660 >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
661
662 int *riser_phy_addr;
663 char *env_hwconfig = env_get("hwconfig");
664
665 if (hwconfig_f("xqsgmii", env_hwconfig))
666 riser_phy_addr = &xqsgii_riser_phy_addr[0];
667 else
668 riser_phy_addr = &sgmii_riser_phy_addr[0];
669
670 if (dpmac_id > WRIOP1_DPMAC9)
671 goto serdes2;
672
673 switch (serdes1_prtcl) {
674 case 0x07:
675 case 0x39:
676 case 0x4D:
677 lane = serdes_get_first_lane(FSL_SRDS_1, SGMII1 + dpmac_id - 1);
678
679 slot = lane_to_slot_fsm1[lane];
680
681 switch (++slot) {
682 case 1:
683 /* Slot housing a SGMII riser card? */
684 wriop_set_phy_address(dpmac_id, 0,
685 riser_phy_addr[dpmac_id - 1]);
686 dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
687 bus = mii_dev_for_muxval(EMI1_SLOT1);
688 wriop_set_mdio(dpmac_id, bus);
689 break;
690 case 2:
691 /* Slot housing a SGMII riser card? */
692 wriop_set_phy_address(dpmac_id, 0,
693 riser_phy_addr[dpmac_id - 1]);
694 dpmac_info[dpmac_id].board_mux = EMI1_SLOT2;
695 bus = mii_dev_for_muxval(EMI1_SLOT2);
696 wriop_set_mdio(dpmac_id, bus);
697 break;
698 case 3:
699 if (slot == EMI_NONE)
700 return;
701 if (serdes1_prtcl == 0x39) {
702 wriop_set_phy_address(dpmac_id, 0,
703 riser_phy_addr[dpmac_id - 2]);
704 if (dpmac_id >= 6 && hwconfig_f("xqsgmii",
705 env_hwconfig))
706 wriop_set_phy_address(dpmac_id, 0,
707 riser_phy_addr[dpmac_id - 3]);
708 } else {
709 wriop_set_phy_address(dpmac_id, 0,
710 riser_phy_addr[dpmac_id - 2]);
711 if (dpmac_id >= 7 && hwconfig_f("xqsgmii",
712 env_hwconfig))
713 wriop_set_phy_address(dpmac_id, 0,
714 riser_phy_addr[dpmac_id - 3]);
715 }
716 dpmac_info[dpmac_id].board_mux = EMI1_SLOT3;
717 bus = mii_dev_for_muxval(EMI1_SLOT3);
718 wriop_set_mdio(dpmac_id, bus);
719 break;
720 case 4:
721 break;
722 case 5:
723 break;
724 case 6:
725 break;
726 }
727 break;
728 default:
729 printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
730 __func__ , serdes1_prtcl);
731 break;
732 }
733
734 serdes2:
735 switch (serdes2_prtcl) {
736 case 0x07:
737 case 0x08:
738 case 0x49:
739 case 0x47:
740 case 0x57:
741 lane = serdes_get_first_lane(FSL_SRDS_2, SGMII9 +
742 (dpmac_id - 9));
743 slot = lane_to_slot_fsm2[lane];
744
745 switch (++slot) {
746 case 1:
747 break;
748 case 3:
749 break;
750 case 4:
751 /* Slot housing a SGMII riser card? */
752 wriop_set_phy_address(dpmac_id, 0,
753 riser_phy_addr[dpmac_id - 9]);
754 dpmac_info[dpmac_id].board_mux = EMI1_SLOT4;
755 bus = mii_dev_for_muxval(EMI1_SLOT4);
756 wriop_set_mdio(dpmac_id, bus);
757 break;
758 case 5:
759 if (slot == EMI_NONE)
760 return;
761 if (serdes2_prtcl == 0x47) {
762 wriop_set_phy_address(dpmac_id, 0,
763 riser_phy_addr[dpmac_id - 10]);
764 if (dpmac_id >= 14 && hwconfig_f("xqsgmii",
765 env_hwconfig))
766 wriop_set_phy_address(dpmac_id, 0,
767 riser_phy_addr[dpmac_id - 11]);
768 } else {
769 wriop_set_phy_address(dpmac_id, 0,
770 riser_phy_addr[dpmac_id - 11]);
771 }
772 dpmac_info[dpmac_id].board_mux = EMI1_SLOT5;
773 bus = mii_dev_for_muxval(EMI1_SLOT5);
774 wriop_set_mdio(dpmac_id, bus);
775 break;
776 case 6:
777 /* Slot housing a SGMII riser card? */
778 wriop_set_phy_address(dpmac_id, 0,
779 riser_phy_addr[dpmac_id - 13]);
780 dpmac_info[dpmac_id].board_mux = EMI1_SLOT6;
781 bus = mii_dev_for_muxval(EMI1_SLOT6);
782 wriop_set_mdio(dpmac_id, bus);
783 break;
784 }
785 break;
786 default:
787 printf("%s qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n",
788 __func__, serdes2_prtcl);
789 break;
790 }
791 }
792
ls2080a_handle_phy_interface_qsgmii(int dpmac_id)793 void ls2080a_handle_phy_interface_qsgmii(int dpmac_id)
794 {
795 int lane = 0, slot;
796 struct mii_dev *bus;
797 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
798 int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
799 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
800 >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
801
802 switch (serdes1_prtcl) {
803 case 0x33:
804 switch (dpmac_id) {
805 case 1:
806 case 2:
807 case 3:
808 case 4:
809 lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_A);
810 break;
811 case 5:
812 case 6:
813 case 7:
814 case 8:
815 lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_B);
816 break;
817 case 9:
818 case 10:
819 case 11:
820 case 12:
821 lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_C);
822 break;
823 case 13:
824 case 14:
825 case 15:
826 case 16:
827 lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_D);
828 break;
829 }
830
831 slot = lane_to_slot_fsm1[lane];
832
833 switch (++slot) {
834 case 1:
835 /* Slot housing a QSGMII riser card? */
836 wriop_set_phy_address(dpmac_id, 0, dpmac_id - 1);
837 dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
838 bus = mii_dev_for_muxval(EMI1_SLOT1);
839 wriop_set_mdio(dpmac_id, bus);
840 break;
841 case 3:
842 break;
843 case 4:
844 break;
845 case 5:
846 break;
847 case 6:
848 break;
849 }
850 break;
851 default:
852 printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
853 serdes1_prtcl);
854 break;
855 }
856
857 qsgmii_configure_repeater(dpmac_id);
858 }
859
ls2080a_handle_phy_interface_xsgmii(int i)860 void ls2080a_handle_phy_interface_xsgmii(int i)
861 {
862 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
863 int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
864 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
865 >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
866
867 switch (serdes1_prtcl) {
868 case 0x2A:
869 case 0x4B:
870 case 0x4C:
871 /*
872 * XFI does not need a PHY to work, but to avoid U-Boot use
873 * default PHY address which is zero to a MAC when it found
874 * a MAC has no PHY address, we give a PHY address to XFI
875 * MAC, and should not use a real XAUI PHY address, since
876 * MDIO can access it successfully, and then MDIO thinks
877 * the XAUI card is used for the XFI MAC, which will cause
878 * error.
879 */
880 wriop_set_phy_address(i, 0, i + 4);
881 ls2080a_qds_enable_SFP_TX(SFP_TX);
882
883 break;
884 default:
885 printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
886 serdes1_prtcl);
887 break;
888 }
889 }
890 #endif
891
board_eth_init(bd_t * bis)892 int board_eth_init(bd_t *bis)
893 {
894 int error;
895 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
896 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
897 int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
898 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
899 >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
900 int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
901 FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
902 >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
903
904 struct memac_mdio_info *memac_mdio0_info;
905 struct memac_mdio_info *memac_mdio1_info;
906 unsigned int i;
907 char *env_hwconfig;
908
909 env_hwconfig = env_get("hwconfig");
910
911 initialize_dpmac_to_slot();
912
913 memac_mdio0_info = (struct memac_mdio_info *)malloc(
914 sizeof(struct memac_mdio_info));
915 memac_mdio0_info->regs =
916 (struct memac_mdio_controller *)
917 CONFIG_SYS_FSL_WRIOP1_MDIO1;
918 memac_mdio0_info->name = DEFAULT_WRIOP_MDIO1_NAME;
919
920 /* Register the real MDIO1 bus */
921 fm_memac_mdio_init(bis, memac_mdio0_info);
922
923 memac_mdio1_info = (struct memac_mdio_info *)malloc(
924 sizeof(struct memac_mdio_info));
925 memac_mdio1_info->regs =
926 (struct memac_mdio_controller *)
927 CONFIG_SYS_FSL_WRIOP1_MDIO2;
928 memac_mdio1_info->name = DEFAULT_WRIOP_MDIO2_NAME;
929
930 /* Register the real MDIO2 bus */
931 fm_memac_mdio_init(bis, memac_mdio1_info);
932
933 /* Register the muxing front-ends to the MDIO buses */
934 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1);
935 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT2);
936 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT3);
937 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT4);
938 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT5);
939 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT6);
940
941 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO2_NAME, EMI2);
942
943 for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
944 switch (wriop_get_enet_if(i)) {
945 case PHY_INTERFACE_MODE_QSGMII:
946 ls2080a_handle_phy_interface_qsgmii(i);
947 break;
948 case PHY_INTERFACE_MODE_SGMII:
949 ls2080a_handle_phy_interface_sgmii(i);
950 break;
951 case PHY_INTERFACE_MODE_XGMII:
952 ls2080a_handle_phy_interface_xsgmii(i);
953 break;
954 default:
955 break;
956
957 if (i == 16)
958 i = NUM_WRIOP_PORTS;
959 }
960 }
961
962 error = cpu_eth_init(bis);
963
964 if (hwconfig_f("xqsgmii", env_hwconfig)) {
965 if (serdes1_prtcl == 0x7)
966 sgmii_configure_repeater(1);
967 if (serdes2_prtcl == 0x7 || serdes2_prtcl == 0x8 ||
968 serdes2_prtcl == 0x49)
969 sgmii_configure_repeater(2);
970 }
971 #endif
972 error = pci_eth_init(bis);
973 return error;
974 }
975
976 #if defined(CONFIG_RESET_PHY_R)
reset_phy(void)977 void reset_phy(void)
978 {
979 mc_env_boot();
980 }
981 #endif /* CONFIG_RESET_PHY_R */
982