1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2004, 2007, 2009-2011 Freescale Semiconductor, Inc.
4 *
5 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
6 */
7
8 #include <common.h>
9 #include <init.h>
10 #include <pci.h>
11 #include <vsprintf.h>
12 #include <asm/processor.h>
13 #include <asm/mmu.h>
14 #include <asm/immap_85xx.h>
15 #include <asm/fsl_pci.h>
16 #include <fsl_ddr_sdram.h>
17 #include <asm/fsl_serdes.h>
18 #include <miiphy.h>
19 #include <linux/libfdt.h>
20 #include <fdt_support.h>
21 #include <tsec.h>
22 #include <fsl_mdio.h>
23 #include <netdev.h>
24
25 #include "../common/cadmus.h"
26 #include "../common/eeprom.h"
27 #include "../common/via.h"
28
29 void local_bus_init(void);
30
checkboard(void)31 int checkboard (void)
32 {
33 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
34 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
35
36 /* PCI slot in USER bits CSR[6:7] by convention. */
37 uint pci_slot = get_pci_slot ();
38
39 uint cpu_board_rev = get_cpu_board_revision ();
40
41 puts("Board: MPC8548CDS");
42 printf(" Carrier Rev: 0x%02x, PCI Slot %d\n",
43 get_board_version(), pci_slot);
44 printf(" Daughtercard Rev: %d.%d (0x%04x)\n",
45 MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
46 MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
47 /*
48 * Initialize local bus.
49 */
50 local_bus_init ();
51
52 /*
53 * Hack TSEC 3 and 4 IO voltages.
54 */
55 gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */
56
57 ecm->eedr = 0xffffffff; /* clear ecm errors */
58 ecm->eeer = 0xffffffff; /* enable ecm errors */
59 return 0;
60 }
61
62 /*
63 * Initialize Local Bus
64 */
65 void
local_bus_init(void)66 local_bus_init(void)
67 {
68 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
69 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
70
71 uint clkdiv;
72 sys_info_t sysinfo;
73
74 get_sys_info(&sysinfo);
75 clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
76
77 gur->lbiuiplldcr1 = 0x00078080;
78 if (clkdiv == 16) {
79 gur->lbiuiplldcr0 = 0x7c0f1bf0;
80 } else if (clkdiv == 8) {
81 gur->lbiuiplldcr0 = 0x6c0f1bf0;
82 } else if (clkdiv == 4) {
83 gur->lbiuiplldcr0 = 0x5c0f1bf0;
84 }
85
86 lbc->lcrr |= 0x00030000;
87
88 asm("sync;isync;msync");
89
90 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
91 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
92 }
93
94 /*
95 * Initialize SDRAM memory on the Local Bus.
96 */
lbc_sdram_init(void)97 void lbc_sdram_init(void)
98 {
99 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
100
101 uint idx;
102 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
103 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
104 uint lsdmr_common;
105
106 puts("LBC SDRAM: ");
107 print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
108 "\n");
109
110 /*
111 * Setup SDRAM Base and Option Registers
112 */
113 set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
114 set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
115 lbc->lbcr = CONFIG_SYS_LBC_LBCR;
116 asm("msync");
117
118 lbc->lsrt = CONFIG_SYS_LBC_LSRT;
119 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
120 asm("msync");
121
122 /*
123 * MPC8548 uses "new" 15-16 style addressing.
124 */
125 lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
126 lsdmr_common |= LSDMR_BSMA1516;
127
128 /*
129 * Issue PRECHARGE ALL command.
130 */
131 lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
132 asm("sync;msync");
133 *sdram_addr = 0xff;
134 ppcDcbf((unsigned long) sdram_addr);
135 udelay(100);
136
137 /*
138 * Issue 8 AUTO REFRESH commands.
139 */
140 for (idx = 0; idx < 8; idx++) {
141 lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
142 asm("sync;msync");
143 *sdram_addr = 0xff;
144 ppcDcbf((unsigned long) sdram_addr);
145 udelay(100);
146 }
147
148 /*
149 * Issue 8 MODE-set command.
150 */
151 lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
152 asm("sync;msync");
153 *sdram_addr = 0xff;
154 ppcDcbf((unsigned long) sdram_addr);
155 udelay(100);
156
157 /*
158 * Issue NORMAL OP command.
159 */
160 lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
161 asm("sync;msync");
162 *sdram_addr = 0xff;
163 ppcDcbf((unsigned long) sdram_addr);
164 udelay(200); /* Overkill. Must wait > 200 bus cycles */
165
166 #endif /* enable SDRAM init */
167 }
168
169 #if (defined(CONFIG_PCI) || defined(CONFIG_PCI1)) && !defined(CONFIG_DM_PCI)
170 /* For some reason the Tundra PCI bridge shows up on itself as a
171 * different device. Work around that by refusing to configure it.
172 */
dummy_func(struct pci_controller * hose,pci_dev_t dev,struct pci_config_table * tab)173 void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
174
175 static struct pci_config_table pci_mpc85xxcds_config_table[] = {
176 {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
177 {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
178 {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
179 mpc85xx_config_via_usbide, {0,0,0}},
180 {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
181 mpc85xx_config_via_usb, {0,0,0}},
182 {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
183 mpc85xx_config_via_usb2, {0,0,0}},
184 {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
185 mpc85xx_config_via_power, {0,0,0}},
186 {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
187 mpc85xx_config_via_ac97, {0,0,0}},
188 {},
189 };
190
191 static struct pci_controller pci1_hose;
192 #endif /* CONFIG_PCI */
193
194 #if !defined(CONFIG_DM_PCI)
pci_init_board(void)195 void pci_init_board(void)
196 {
197 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
198 struct fsl_pci_info pci_info;
199 u32 devdisr, pordevsr, io_sel;
200 u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
201 int first_free_busno = 0;
202 char buf[32];
203
204 devdisr = in_be32(&gur->devdisr);
205 pordevsr = in_be32(&gur->pordevsr);
206 porpllsr = in_be32(&gur->porpllsr);
207 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
208
209 debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
210
211 #ifdef CONFIG_PCI1
212 pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
213 pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
214 pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
215 pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
216
217 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
218 SET_STD_PCI_INFO(pci_info, 1);
219 set_next_law(pci_info.mem_phys,
220 law_size_bits(pci_info.mem_size), pci_info.law);
221 set_next_law(pci_info.io_phys,
222 law_size_bits(pci_info.io_size), pci_info.law);
223
224 pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
225 printf("PCI1: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
226 (pci_32) ? 32 : 64,
227 strmhz(buf, pci_speed),
228 pci_clk_sel ? "sync" : "async",
229 pci_agent ? "agent" : "host",
230 pci_arb ? "arbiter" : "external-arbiter",
231 pci_info.regs);
232
233 pci1_hose.config_table = pci_mpc85xxcds_config_table;
234 first_free_busno = fsl_pci_init_port(&pci_info,
235 &pci1_hose, first_free_busno);
236
237 #ifdef CONFIG_PCIX_CHECK
238 if (!(pordevsr & MPC85xx_PORDEVSR_PCI1)) {
239 /* PCI-X init */
240 if (CONFIG_SYS_CLK_FREQ < 66000000)
241 printf("PCI-X will only work at 66 MHz\n");
242
243 reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
244 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
245 pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16);
246 }
247 #endif
248 } else {
249 printf("PCI1: disabled\n");
250 }
251
252 puts("\n");
253 #else
254 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
255 #endif
256
257 #ifdef CONFIG_PCI2
258 {
259 uint pci2_clk_sel = porpllsr & 0x4000; /* PORPLLSR[17] */
260 uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
261 if (pci_dual) {
262 printf("PCI2: 32 bit, 66 MHz, %s\n",
263 pci2_clk_sel ? "sync" : "async");
264 } else {
265 printf("PCI2: disabled\n");
266 }
267 }
268 #else
269 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable */
270 #endif /* CONFIG_PCI2 */
271
272 fsl_pcie_init_board(first_free_busno);
273 }
274 #endif
275
configure_rgmii(void)276 void configure_rgmii(void)
277 {
278 unsigned short temp;
279
280 /* Change the resistors for the PHY */
281 /* This is needed to get the RGMII working for the 1.3+
282 * CDS cards */
283 if (get_board_version() == 0x13) {
284 miiphy_write(DEFAULT_MII_NAME,
285 TSEC1_PHY_ADDR, 29, 18);
286
287 miiphy_read(DEFAULT_MII_NAME,
288 TSEC1_PHY_ADDR, 30, &temp);
289
290 temp = (temp & 0xf03f);
291 temp |= 2 << 9; /* 36 ohm */
292 temp |= 2 << 6; /* 39 ohm */
293
294 miiphy_write(DEFAULT_MII_NAME,
295 TSEC1_PHY_ADDR, 30, temp);
296
297 miiphy_write(DEFAULT_MII_NAME,
298 TSEC1_PHY_ADDR, 29, 3);
299
300 miiphy_write(DEFAULT_MII_NAME,
301 TSEC1_PHY_ADDR, 30, 0x8000);
302 }
303
304 return;
305 }
306
board_eth_init(bd_t * bis)307 int board_eth_init(bd_t *bis)
308 {
309 #ifdef CONFIG_TSEC_ENET
310 struct fsl_pq_mdio_info mdio_info;
311 struct tsec_info_struct tsec_info[4];
312 int num = 0;
313
314 #ifdef CONFIG_TSEC1
315 SET_STD_TSEC_INFO(tsec_info[num], 1);
316 num++;
317 #endif
318 #ifdef CONFIG_TSEC2
319 SET_STD_TSEC_INFO(tsec_info[num], 2);
320 num++;
321 #endif
322 #ifdef CONFIG_TSEC3
323 /* initialize TSEC3 only if Carrier is 1.3 or above on CDS */
324 if (get_board_version() >= 0x13) {
325 SET_STD_TSEC_INFO(tsec_info[num], 3);
326 tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID;
327 num++;
328 }
329 #endif
330 #ifdef CONFIG_TSEC4
331 /* initialize TSEC4 only if Carrier is 1.3 or above on CDS */
332 if (get_board_version() >= 0x13) {
333 SET_STD_TSEC_INFO(tsec_info[num], 4);
334 tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID;
335 num++;
336 }
337 #endif
338
339 if (!num) {
340 printf("No TSECs initialized\n");
341
342 return 0;
343 }
344
345 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
346 mdio_info.name = DEFAULT_MII_NAME;
347 fsl_pq_mdio_init(bis, &mdio_info);
348
349 tsec_eth_init(bis, tsec_info, num);
350 configure_rgmii();
351 #endif
352
353 return pci_eth_init(bis);
354 }
355
356 #if defined(CONFIG_OF_BOARD_SETUP) && !defined(CONFIG_DM_PCI)
ft_pci_setup(void * blob,bd_t * bd)357 void ft_pci_setup(void *blob, bd_t *bd)
358 {
359 FT_FSL_PCI_SETUP;
360 }
361 #endif
362