1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2007 Freescale Semiconductor. 4 */ 5 6 #ifndef __BCSR_H_ 7 #define __BCSR_H_ 8 9 #include <common.h> 10 11 /* BCSR Bit definitions 12 * BCSR 0 * 13 0:3 ccb sys pll 14 4:6 cfg core pll 15 7 cfg boot seq 16 17 * BCSR 1 * 18 0:2 cfg rom lock 19 3:5 cfg host agent 20 6 PCI IO 21 7 cfg RIO size 22 23 * BCSR 2 * 24 0:4 QE PLL 25 5 QE clock 26 6 cfg PCI arbiter 27 28 * BCSR 3 * 29 0 TSEC1 reduce 30 1 TSEC2 reduce 31 2:3 TSEC1 protocol 32 4:5 TSEC2 protocol 33 6 PHY1 slave 34 7 PHY2 slave 35 36 * BCSR 4 * 37 4 clock enable 38 5 boot EPROM 39 6 GETH transactive reset 40 7 BRD write potect 41 42 * BCSR 5 * 43 1:3 Leds 1-3 44 4 UPC1 enable 45 5 UPC2 enable 46 6 UPC2 pos 47 7 RS232 enable 48 49 * BCSR 6 * 50 0 CFG ver 0 51 1 CFG ver 1 52 6 Register config led 53 7 Power on reset 54 55 * BCSR 7 * 56 2 board host mode indication 57 5 enable TSEC1 PHY 58 6 enable TSEC2 PHY 59 60 * BCSR 8 * 61 0 UCC GETH1 enable 62 1 UCC GMII enable 63 3 UCC TBI enable 64 5 UCC MII enable 65 7 Real time clock reset 66 67 * BCSR 9 * 68 0 UCC2 GETH enable 69 1 UCC2 GMII enable 70 3 UCC2 TBI enable 71 5 UCC2 MII enable 72 6 Ready only - indicate flash ready after burning 73 7 Flash write protect 74 */ 75 76 #define BCSR_UCC1_GETH_EN (0x1 << 7) 77 #define BCSR_UCC2_GETH_EN (0x1 << 7) 78 #define BCSR_UCC1_MODE_MSK (0x3 << 4) 79 #define BCSR_UCC2_MODE_MSK (0x3 << 0) 80 81 /*BCSR Utils functions*/ 82 83 void enable_8568mds_duart(void); 84 void enable_8568mds_flash_write(void); 85 void disable_8568mds_flash_write(void); 86 void enable_8568mds_qe_mdio(void); 87 88 #if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2) 89 void reset_8568mds_uccs(void); 90 #endif 91 92 #endif /* __BCSR_H_ */ 93