1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2014 Freescale Semiconductor, Inc.
4 *
5 * Author: Fabio Estevam <fabio.estevam@freescale.com>
6 */
7
8 #include <init.h>
9 #include <asm/arch/clock.h>
10 #include <asm/arch/crm_regs.h>
11 #include <asm/arch/iomux.h>
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/mx6-pins.h>
14 #include <asm/arch/sys_proto.h>
15 #include <asm/gpio.h>
16 #include <asm/mach-imx/iomux-v3.h>
17 #include <asm/io.h>
18 #include <asm/mach-imx/mxc_i2c.h>
19 #include <env.h>
20 #include <linux/sizes.h>
21 #include <common.h>
22 #include <fsl_esdhc_imx.h>
23 #include <mmc.h>
24 #include <i2c.h>
25 #include <miiphy.h>
26 #include <netdev.h>
27 #include <power/pmic.h>
28 #include <power/pfuze100_pmic.h>
29 #include "../common/pfuze.h"
30
31 DECLARE_GLOBAL_DATA_PTR;
32
33 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
34 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
35 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
36
37 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
38 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
39 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
40
41 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
42 PAD_CTL_SPEED_HIGH | \
43 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
44
45 #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
46 PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
47
48 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
49 PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
50
51 #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
52 PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
53
54 #define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | \
55 PAD_CTL_DSE_40ohm)
56
dram_init(void)57 int dram_init(void)
58 {
59 gd->ram_size = imx_ddr_size();
60
61 return 0;
62 }
63
64 static iomux_v3_cfg_t const uart1_pads[] = {
65 MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
66 MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
67 };
68
69 static iomux_v3_cfg_t const wdog_b_pad = {
70 MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL),
71 };
72 static iomux_v3_cfg_t const fec1_pads[] = {
73 MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
74 MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
75 MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
76 MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
77 MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
78 MX6_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
79 MX6_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
80 MX6_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
81 MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
82 MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
83 MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
84 MX6_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
85 MX6_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
86 MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
87 };
88
89 static iomux_v3_cfg_t const peri_3v3_pads[] = {
90 MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL),
91 };
92
93 static iomux_v3_cfg_t const phy_control_pads[] = {
94 /* 25MHz Ethernet PHY Clock */
95 MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
96
97 /* ENET PHY Power */
98 MX6_PAD_ENET2_COL__GPIO2_IO_6 | MUX_PAD_CTRL(NO_PAD_CTRL),
99
100 /* AR8031 PHY Reset */
101 MX6_PAD_ENET2_CRS__GPIO2_IO_7 | MUX_PAD_CTRL(NO_PAD_CTRL),
102 };
103
setup_iomux_uart(void)104 static void setup_iomux_uart(void)
105 {
106 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
107 }
108
setup_fec(void)109 static int setup_fec(void)
110 {
111 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
112 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
113 int reg, ret;
114
115 /* Use 125MHz anatop loopback REF_CLK1 for ENET1 */
116 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0);
117
118 ret = enable_fec_anatop_clock(0, ENET_125MHZ);
119 if (ret)
120 return ret;
121
122 imx_iomux_v3_setup_multiple_pads(phy_control_pads,
123 ARRAY_SIZE(phy_control_pads));
124
125 /* Enable the ENET power, active low */
126 gpio_request(IMX_GPIO_NR(2, 6), "enet_rst");
127 gpio_direction_output(IMX_GPIO_NR(2, 6) , 0);
128
129 /* Reset AR8031 PHY */
130 gpio_request(IMX_GPIO_NR(2, 7), "phy_rst");
131 gpio_direction_output(IMX_GPIO_NR(2, 7) , 0);
132 mdelay(10);
133 gpio_set_value(IMX_GPIO_NR(2, 7), 1);
134
135 reg = readl(&anatop->pll_enet);
136 reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
137 writel(reg, &anatop->pll_enet);
138
139 return 0;
140 }
141
board_eth_init(bd_t * bis)142 int board_eth_init(bd_t *bis)
143 {
144 imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
145 setup_fec();
146
147 return cpu_eth_init(bis);
148 }
149
power_init_board(void)150 int power_init_board(void)
151 {
152 struct udevice *dev;
153 unsigned int reg;
154 int ret;
155
156 dev = pfuze_common_init();
157 if (!dev)
158 return -ENODEV;
159
160 ret = pfuze_mode_init(dev, APS_PFM);
161 if (ret < 0)
162 return ret;
163
164 /* Enable power of VGEN5 3V3, needed for SD3 */
165 reg = pmic_reg_read(dev, PFUZE100_VGEN5VOL);
166 reg &= ~LDO_VOL_MASK;
167 reg |= (LDOB_3_30V | (1 << LDO_EN));
168 pmic_reg_write(dev, PFUZE100_VGEN5VOL, reg);
169
170 return 0;
171 }
172
board_phy_config(struct phy_device * phydev)173 int board_phy_config(struct phy_device *phydev)
174 {
175 /*
176 * Enable 1.8V(SEL_1P5_1P8_POS_REG) on
177 * Phy control debug reg 0
178 */
179 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
180 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
181
182 /* rgmii tx clock delay enable */
183 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
184 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
185
186 if (phydev->drv->config)
187 phydev->drv->config(phydev);
188
189 return 0;
190 }
191
board_early_init_f(void)192 int board_early_init_f(void)
193 {
194 setup_iomux_uart();
195
196 /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */
197 imx_iomux_v3_setup_multiple_pads(peri_3v3_pads,
198 ARRAY_SIZE(peri_3v3_pads));
199
200 return 0;
201 }
202
board_mmc_get_env_dev(int devno)203 int board_mmc_get_env_dev(int devno)
204 {
205 return devno;
206 }
207
208 #ifdef CONFIG_FSL_QSPI
209
board_qspi_init(void)210 int board_qspi_init(void)
211 {
212 /* Set the clock */
213 enable_qspi_clk(1);
214
215 return 0;
216 }
217 #endif
218
219 #ifdef CONFIG_VIDEO_MXS
220 static iomux_v3_cfg_t const lcd_pads[] = {
221 MX6_PAD_LCD1_CLK__LCDIF1_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
222 MX6_PAD_LCD1_ENABLE__LCDIF1_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
223 MX6_PAD_LCD1_HSYNC__LCDIF1_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
224 MX6_PAD_LCD1_VSYNC__LCDIF1_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
225 MX6_PAD_LCD1_DATA00__LCDIF1_DATA_0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
226 MX6_PAD_LCD1_DATA01__LCDIF1_DATA_1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
227 MX6_PAD_LCD1_DATA02__LCDIF1_DATA_2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
228 MX6_PAD_LCD1_DATA03__LCDIF1_DATA_3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
229 MX6_PAD_LCD1_DATA04__LCDIF1_DATA_4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
230 MX6_PAD_LCD1_DATA05__LCDIF1_DATA_5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
231 MX6_PAD_LCD1_DATA06__LCDIF1_DATA_6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
232 MX6_PAD_LCD1_DATA07__LCDIF1_DATA_7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
233 MX6_PAD_LCD1_DATA08__LCDIF1_DATA_8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
234 MX6_PAD_LCD1_DATA09__LCDIF1_DATA_9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
235 MX6_PAD_LCD1_DATA10__LCDIF1_DATA_10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
236 MX6_PAD_LCD1_DATA11__LCDIF1_DATA_11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
237 MX6_PAD_LCD1_DATA12__LCDIF1_DATA_12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
238 MX6_PAD_LCD1_DATA13__LCDIF1_DATA_13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
239 MX6_PAD_LCD1_DATA14__LCDIF1_DATA_14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
240 MX6_PAD_LCD1_DATA15__LCDIF1_DATA_15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
241 MX6_PAD_LCD1_DATA16__LCDIF1_DATA_16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
242 MX6_PAD_LCD1_DATA17__LCDIF1_DATA_17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
243 MX6_PAD_LCD1_DATA18__LCDIF1_DATA_18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
244 MX6_PAD_LCD1_DATA19__LCDIF1_DATA_19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
245 MX6_PAD_LCD1_DATA20__LCDIF1_DATA_20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
246 MX6_PAD_LCD1_DATA21__LCDIF1_DATA_21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
247 MX6_PAD_LCD1_DATA22__LCDIF1_DATA_22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
248 MX6_PAD_LCD1_DATA23__LCDIF1_DATA_23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
249 MX6_PAD_LCD1_RESET__GPIO3_IO_27 | MUX_PAD_CTRL(NO_PAD_CTRL),
250
251 /* Use GPIO for Brightness adjustment, duty cycle = period */
252 MX6_PAD_SD1_DATA2__GPIO6_IO_4 | MUX_PAD_CTRL(NO_PAD_CTRL),
253 };
254
setup_lcd(void)255 static int setup_lcd(void)
256 {
257 enable_lcdif_clock(LCDIF1_BASE_ADDR, 1);
258
259 imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
260
261 /* Reset the LCD */
262 gpio_request(IMX_GPIO_NR(3, 27), "lcd_rst");
263 gpio_direction_output(IMX_GPIO_NR(3, 27) , 0);
264 udelay(500);
265 gpio_direction_output(IMX_GPIO_NR(3, 27) , 1);
266
267 /* Set Brightness to high */
268 gpio_request(IMX_GPIO_NR(6, 4), "lcd_bright");
269 gpio_direction_output(IMX_GPIO_NR(6, 4) , 1);
270
271 return 0;
272 }
273 #endif
274
board_init(void)275 int board_init(void)
276 {
277 /* Address of boot parameters */
278 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
279
280 /*
281 * Because kernel set WDOG_B mux before pad with the common pinctrl
282 * framwork now and wdog reset will be triggered once set WDOG_B mux
283 * with default pad setting, we set pad setting here to workaround this.
284 * Since imx_iomux_v3_setup_pad also set mux before pad setting, we set
285 * as GPIO mux firstly here to workaround it.
286 */
287 imx_iomux_v3_setup_pad(wdog_b_pad);
288
289 /* Active high for ncp692 */
290 gpio_request(IMX_GPIO_NR(4, 16), "ncp692_en");
291 gpio_direction_output(IMX_GPIO_NR(4, 16), 1);
292
293 #ifdef CONFIG_FSL_QSPI
294 board_qspi_init();
295 #endif
296
297 #ifdef CONFIG_VIDEO_MXS
298 setup_lcd();
299 #endif
300
301 return 0;
302 }
303
is_reva(void)304 static bool is_reva(void)
305 {
306 return (nxp_board_rev() == 1);
307 }
308
board_late_init(void)309 int board_late_init(void)
310 {
311 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
312 if (is_reva())
313 env_set("board_rev", "REVA");
314 #endif
315 return 0;
316 }
317
checkboard(void)318 int checkboard(void)
319 {
320 printf("Board: MX6SX SABRE SDB rev%c\n", nxp_board_rev_string());
321
322 return 0;
323 }
324
325 #ifdef CONFIG_SPL_BUILD
326 #include <linux/libfdt.h>
327 #include <spl.h>
328 #include <asm/arch/mx6-ddr.h>
329
330 static struct fsl_esdhc_cfg usdhc_cfg[3] = {
331 {USDHC2_BASE_ADDR, 0, 4},
332 {USDHC3_BASE_ADDR},
333 {USDHC4_BASE_ADDR},
334 };
335
336 #define USDHC3_CD_GPIO IMX_GPIO_NR(2, 10)
337 #define USDHC3_PWR_GPIO IMX_GPIO_NR(2, 11)
338 #define USDHC4_CD_GPIO IMX_GPIO_NR(6, 21)
339
340 static iomux_v3_cfg_t const usdhc2_pads[] = {
341 MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
342 MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
343 MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
344 MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
345 MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
346 MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
347 };
348
349 static iomux_v3_cfg_t const usdhc3_pads[] = {
350 MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
351 MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
352 MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
353 MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
354 MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
355 MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
356 MX6_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
357 MX6_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
358 MX6_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
359 MX6_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
360
361 /* CD pin */
362 MX6_PAD_KEY_COL0__GPIO2_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL),
363
364 /* RST_B, used for power reset cycle */
365 MX6_PAD_KEY_COL1__GPIO2_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL),
366 };
367
368 static iomux_v3_cfg_t const usdhc4_pads[] = {
369 MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
370 MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
371 MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
372 MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
373 MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
374 MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
375 MX6_PAD_SD4_DATA7__GPIO6_IO_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
376 };
377
board_mmc_init(bd_t * bis)378 int board_mmc_init(bd_t *bis)
379 {
380 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
381 u32 val;
382 u32 port;
383
384 val = readl(&src_regs->sbmr1);
385
386 if ((val & 0xc0) != 0x40) {
387 printf("Not boot from USDHC!\n");
388 return -EINVAL;
389 }
390
391 port = (val >> 11) & 0x3;
392 printf("port %d\n", port);
393 switch (port) {
394 case 1:
395 imx_iomux_v3_setup_multiple_pads(
396 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
397 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
398 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
399 break;
400 case 2:
401 imx_iomux_v3_setup_multiple_pads(
402 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
403 gpio_direction_input(USDHC3_CD_GPIO);
404 gpio_direction_output(USDHC3_PWR_GPIO, 1);
405 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
406 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
407 break;
408 case 3:
409 imx_iomux_v3_setup_multiple_pads(
410 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
411 gpio_direction_input(USDHC4_CD_GPIO);
412 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
413 usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
414 break;
415 }
416
417 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
418 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
419 }
420
board_mmc_getcd(struct mmc * mmc)421 int board_mmc_getcd(struct mmc *mmc)
422 {
423 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
424 int ret = 0;
425
426 switch (cfg->esdhc_base) {
427 case USDHC2_BASE_ADDR:
428 ret = 1; /* Assume uSDHC2 is always present */
429 break;
430 case USDHC3_BASE_ADDR:
431 ret = !gpio_get_value(USDHC3_CD_GPIO);
432 break;
433 case USDHC4_BASE_ADDR:
434 ret = !gpio_get_value(USDHC4_CD_GPIO);
435 break;
436 }
437
438 return ret;
439 }
440
441 const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = {
442 .dram_dqm0 = 0x00000028,
443 .dram_dqm1 = 0x00000028,
444 .dram_dqm2 = 0x00000028,
445 .dram_dqm3 = 0x00000028,
446 .dram_ras = 0x00000020,
447 .dram_cas = 0x00000020,
448 .dram_odt0 = 0x00000020,
449 .dram_odt1 = 0x00000020,
450 .dram_sdba2 = 0x00000000,
451 .dram_sdcke0 = 0x00003000,
452 .dram_sdcke1 = 0x00003000,
453 .dram_sdclk_0 = 0x00000030,
454 .dram_sdqs0 = 0x00000028,
455 .dram_sdqs1 = 0x00000028,
456 .dram_sdqs2 = 0x00000028,
457 .dram_sdqs3 = 0x00000028,
458 .dram_reset = 0x00000020,
459 };
460
461 const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = {
462 .grp_addds = 0x00000020,
463 .grp_ddrmode_ctl = 0x00020000,
464 .grp_ddrpke = 0x00000000,
465 .grp_ddrmode = 0x00020000,
466 .grp_b0ds = 0x00000028,
467 .grp_b1ds = 0x00000028,
468 .grp_ctlds = 0x00000020,
469 .grp_ddr_type = 0x000c0000,
470 .grp_b2ds = 0x00000028,
471 .grp_b3ds = 0x00000028,
472 };
473
474 const struct mx6_mmdc_calibration mx6_mmcd_calib = {
475 .p0_mpwldectrl0 = 0x00290025,
476 .p0_mpwldectrl1 = 0x00220022,
477 .p0_mpdgctrl0 = 0x41480144,
478 .p0_mpdgctrl1 = 0x01340130,
479 .p0_mprddlctl = 0x3C3E4244,
480 .p0_mpwrdlctl = 0x34363638,
481 };
482
483 static struct mx6_ddr3_cfg mem_ddr = {
484 .mem_speed = 1600,
485 .density = 4,
486 .width = 32,
487 .banks = 8,
488 .rowaddr = 15,
489 .coladdr = 10,
490 .pagesz = 2,
491 .trcd = 1375,
492 .trcmin = 4875,
493 .trasmin = 3500,
494 };
495
ccgr_init(void)496 static void ccgr_init(void)
497 {
498 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
499
500 writel(0xFFFFFFFF, &ccm->CCGR0);
501 writel(0xFFFFFFFF, &ccm->CCGR1);
502 writel(0xFFFFFFFF, &ccm->CCGR2);
503 writel(0xFFFFFFFF, &ccm->CCGR3);
504 writel(0xFFFFFFFF, &ccm->CCGR4);
505 writel(0xFFFFFFFF, &ccm->CCGR5);
506 writel(0xFFFFFFFF, &ccm->CCGR6);
507 writel(0xFFFFFFFF, &ccm->CCGR7);
508 }
509
spl_dram_init(void)510 static void spl_dram_init(void)
511 {
512 struct mx6_ddr_sysinfo sysinfo = {
513 .dsize = mem_ddr.width/32,
514 .cs_density = 24,
515 .ncs = 1,
516 .cs1_mirror = 0,
517 .rtt_wr = 2,
518 .rtt_nom = 2, /* RTT_Nom = RZQ/2 */
519 .walat = 1, /* Write additional latency */
520 .ralat = 5, /* Read additional latency */
521 .mif3_mode = 3, /* Command prediction working mode */
522 .bi_on = 1, /* Bank interleaving enabled */
523 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
524 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
525 .ddr_type = DDR_TYPE_DDR3,
526 .refsel = 1, /* Refresh cycles at 32KHz */
527 .refr = 7, /* 8 refresh commands per refresh cycle */
528 };
529
530 mx6sx_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
531 mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
532 }
533
board_init_f(ulong dummy)534 void board_init_f(ulong dummy)
535 {
536 /* setup AIPS and disable watchdog */
537 arch_cpu_init();
538
539 ccgr_init();
540
541 /* iomux and setup of i2c */
542 board_early_init_f();
543
544 /* setup GP timer */
545 timer_init();
546
547 /* UART clocks enabled and gd valid - init serial console */
548 preloader_console_init();
549
550 /* DDR initialization */
551 spl_dram_init();
552
553 /* Clear the BSS. */
554 memset(__bss_start, 0, __bss_end - __bss_start);
555
556 /* load/boot image from boot device */
557 board_init_r(NULL, 0);
558 }
559 #endif
560