1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2015 Freescale Semiconductor, Inc.
4 */
5
6 #include <init.h>
7 #include <asm/arch/clock.h>
8 #include <asm/arch/iomux.h>
9 #include <asm/arch/imx-regs.h>
10 #include <asm/arch/crm_regs.h>
11 #include <asm/arch/mx6ul_pins.h>
12 #include <asm/arch/mx6-pins.h>
13 #include <asm/arch/sys_proto.h>
14 #include <asm/gpio.h>
15 #include <asm/mach-imx/iomux-v3.h>
16 #include <asm/mach-imx/boot_mode.h>
17 #include <asm/mach-imx/mxc_i2c.h>
18 #include <asm/io.h>
19 #include <common.h>
20 #include <env.h>
21 #include <fsl_esdhc_imx.h>
22 #include <i2c.h>
23 #include <miiphy.h>
24 #include <linux/sizes.h>
25 #include <mmc.h>
26 #include <netdev.h>
27 #include <power/pmic.h>
28 #include <power/pfuze3000_pmic.h>
29 #include "../common/pfuze.h"
30 #include <usb.h>
31 #include <usb/ehci-ci.h>
32
33 DECLARE_GLOBAL_DATA_PTR;
34
35 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
36 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
37 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
38
39 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
40 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
41 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
42
43 #define USDHC_DAT3_CD_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
44 PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \
45 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
46
47 #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
48 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
49 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
50 PAD_CTL_ODE)
51
52 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
53 PAD_CTL_SPEED_HIGH | \
54 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
55
56 #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
57 PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
58
59 #define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
60 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
61
62 #define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
63
64 #define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
65 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
66 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
67
68 #ifdef CONFIG_DM_PMIC
power_init_board(void)69 int power_init_board(void)
70 {
71 struct udevice *dev;
72 int ret, dev_id, rev_id;
73 unsigned int reg;
74
75 ret = pmic_get("pfuze3000", &dev);
76 if (ret == -ENODEV)
77 return 0;
78 if (ret != 0)
79 return ret;
80
81 dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
82 rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
83 printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
84
85 /* disable Low Power Mode during standby mode */
86 reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL);
87 reg |= 0x1;
88 pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg);
89
90 /* SW1B step ramp up time from 2us to 4us/25mV */
91 pmic_reg_write(dev, PFUZE3000_SW1BCONF, 0x40);
92
93 /* SW1B mode to APS/PFM */
94 pmic_reg_write(dev, PFUZE3000_SW1BMODE, 0xc);
95
96 /* SW1B standby voltage set to 0.975V */
97 pmic_reg_write(dev, PFUZE3000_SW1BSTBY, 0xb);
98
99 return 0;
100 }
101 #endif
102
dram_init(void)103 int dram_init(void)
104 {
105 gd->ram_size = imx_ddr_size();
106
107 return 0;
108 }
109
110 static iomux_v3_cfg_t const uart1_pads[] = {
111 MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
112 MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
113 };
114
115 static iomux_v3_cfg_t const usdhc1_pads[] = {
116 MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
117 MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
118 MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
119 MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
120 MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
121 MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
122
123 /* VSELECT */
124 MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
125 /* CD */
126 MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
127 /* RST_B */
128 MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
129 };
130
131 /*
132 * mx6ul_14x14_evk board default supports sd card. If want to use
133 * EMMC, need to do board rework for sd2.
134 * Introduce CONFIG_MX6UL_14X14_EVK_EMMC_REWORK, if sd2 reworked to support
135 * emmc, need to define this macro.
136 */
137 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
138 static iomux_v3_cfg_t const usdhc2_emmc_pads[] = {
139 MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
140 MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
141 MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
142 MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
143 MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
144 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
145 MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
146 MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
147 MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
148 MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
149
150 /*
151 * RST_B
152 */
153 MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
154 };
155 #else
156 static iomux_v3_cfg_t const usdhc2_pads[] = {
157 MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
158 MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
159 MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
160 MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
161 MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
162 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
163 };
164
165 /*
166 * The evk board uses DAT3 to detect CD card plugin,
167 * in u-boot we mux the pin to GPIO when doing board_mmc_getcd.
168 */
169 static iomux_v3_cfg_t const usdhc2_cd_pad =
170 MX6_PAD_NAND_DATA03__GPIO4_IO05 | MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL);
171
172 static iomux_v3_cfg_t const usdhc2_dat3_pad =
173 MX6_PAD_NAND_DATA03__USDHC2_DATA3 |
174 MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL);
175 #endif
176
setup_iomux_uart(void)177 static void setup_iomux_uart(void)
178 {
179 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
180 }
181
182 #ifdef CONFIG_FSL_QSPI
board_qspi_init(void)183 static int board_qspi_init(void)
184 {
185 /* Set the clock */
186 enable_qspi_clk(0);
187
188 return 0;
189 }
190 #endif
191
192 #ifdef CONFIG_FSL_ESDHC_IMX
193 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
194 {USDHC1_BASE_ADDR, 0, 4},
195 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
196 {USDHC2_BASE_ADDR, 0, 8},
197 #else
198 {USDHC2_BASE_ADDR, 0, 4},
199 #endif
200 };
201
202 #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19)
203 #define USDHC1_PWR_GPIO IMX_GPIO_NR(1, 9)
204 #define USDHC2_CD_GPIO IMX_GPIO_NR(4, 5)
205 #define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 10)
206
board_mmc_getcd(struct mmc * mmc)207 int board_mmc_getcd(struct mmc *mmc)
208 {
209 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
210 int ret = 0;
211
212 switch (cfg->esdhc_base) {
213 case USDHC1_BASE_ADDR:
214 ret = !gpio_get_value(USDHC1_CD_GPIO);
215 break;
216 case USDHC2_BASE_ADDR:
217 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
218 ret = 1;
219 #else
220 imx_iomux_v3_setup_pad(usdhc2_cd_pad);
221 gpio_request(USDHC2_CD_GPIO, "usdhc2 cd");
222 gpio_direction_input(USDHC2_CD_GPIO);
223
224 /*
225 * Since it is the DAT3 pin, this pin is pulled to
226 * low voltage if no card
227 */
228 ret = gpio_get_value(USDHC2_CD_GPIO);
229
230 imx_iomux_v3_setup_pad(usdhc2_dat3_pad);
231 #endif
232 break;
233 }
234
235 return ret;
236 }
237
board_mmc_init(bd_t * bis)238 int board_mmc_init(bd_t *bis)
239 {
240 int i, ret;
241
242 /*
243 * According to the board_mmc_init() the following map is done:
244 * (U-Boot device node) (Physical Port)
245 * mmc0 USDHC1
246 * mmc1 USDHC2
247 */
248 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
249 switch (i) {
250 case 0:
251 imx_iomux_v3_setup_multiple_pads(
252 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
253 gpio_request(USDHC1_CD_GPIO, "usdhc1 cd");
254 gpio_direction_input(USDHC1_CD_GPIO);
255 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
256
257 gpio_direction_output(USDHC1_PWR_GPIO, 0);
258 udelay(500);
259 gpio_direction_output(USDHC1_PWR_GPIO, 1);
260 break;
261 case 1:
262 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
263 imx_iomux_v3_setup_multiple_pads(
264 usdhc2_emmc_pads, ARRAY_SIZE(usdhc2_emmc_pads));
265 #else
266 imx_iomux_v3_setup_multiple_pads(
267 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
268 #endif
269 gpio_request(USDHC2_PWR_GPIO, "usdhc2 pwr");
270 gpio_direction_output(USDHC2_PWR_GPIO, 0);
271 udelay(500);
272 gpio_direction_output(USDHC2_PWR_GPIO, 1);
273 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
274 break;
275 default:
276 printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n", i + 1);
277 return -EINVAL;
278 }
279
280 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
281 if (ret) {
282 printf("Warning: failed to initialize mmc dev %d\n", i);
283 return ret;
284 }
285 }
286 return 0;
287 }
288 #endif
289
290 #ifdef CONFIG_USB_EHCI_MX6
291 #ifndef CONFIG_DM_USB
292
293 #define USB_OTHERREGS_OFFSET 0x800
294 #define UCTRL_PWR_POL (1 << 9)
295
296 static iomux_v3_cfg_t const usb_otg_pads[] = {
297 MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
298 };
299
300 /* At default the 3v3 enables the MIC2026 for VBUS power */
setup_usb(void)301 static void setup_usb(void)
302 {
303 imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
304 ARRAY_SIZE(usb_otg_pads));
305 }
306
board_usb_phy_mode(int port)307 int board_usb_phy_mode(int port)
308 {
309 if (port == 1)
310 return USB_INIT_HOST;
311 else
312 return usb_phy_mode(port);
313 }
314
board_ehci_hcd_init(int port)315 int board_ehci_hcd_init(int port)
316 {
317 u32 *usbnc_usb_ctrl;
318
319 if (port > 1)
320 return -EINVAL;
321
322 usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
323 port * 4);
324
325 /* Set Power polarity */
326 setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
327
328 return 0;
329 }
330 #endif
331 #endif
332
333 #ifdef CONFIG_FEC_MXC
334 /*
335 * pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only
336 * be used for ENET1 or ENET2, cannot be used for both.
337 */
338 static iomux_v3_cfg_t const fec1_pads[] = {
339 MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
340 MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
341 MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
342 MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
343 MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
344 MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
345 MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
346 MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
347 MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
348 MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
349 };
350
351 static iomux_v3_cfg_t const fec2_pads[] = {
352 MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
353 MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
354
355 MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
356 MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
357 MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
358 MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
359
360 MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
361 MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
362 MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
363 MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
364 };
365
setup_iomux_fec(int fec_id)366 static void setup_iomux_fec(int fec_id)
367 {
368 if (fec_id == 0)
369 imx_iomux_v3_setup_multiple_pads(fec1_pads,
370 ARRAY_SIZE(fec1_pads));
371 else
372 imx_iomux_v3_setup_multiple_pads(fec2_pads,
373 ARRAY_SIZE(fec2_pads));
374 }
375
board_eth_init(bd_t * bis)376 int board_eth_init(bd_t *bis)
377 {
378 setup_iomux_fec(CONFIG_FEC_ENET_DEV);
379
380 return fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
381 CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
382 }
383
setup_fec(int fec_id)384 static int setup_fec(int fec_id)
385 {
386 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
387 int ret;
388
389 if (fec_id == 0) {
390 /*
391 * Use 50M anatop loopback REF_CLK1 for ENET1,
392 * clear gpr1[13], set gpr1[17].
393 */
394 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
395 IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
396 } else {
397 /*
398 * Use 50M anatop loopback REF_CLK2 for ENET2,
399 * clear gpr1[14], set gpr1[18].
400 */
401 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
402 IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
403 }
404
405 ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
406 if (ret)
407 return ret;
408
409 enable_enet_clk(1);
410
411 return 0;
412 }
413
board_phy_config(struct phy_device * phydev)414 int board_phy_config(struct phy_device *phydev)
415 {
416 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
417
418 if (phydev->drv->config)
419 phydev->drv->config(phydev);
420
421 return 0;
422 }
423 #endif
424
425 #ifdef CONFIG_DM_VIDEO
426 static iomux_v3_cfg_t const lcd_pads[] = {
427 /* Use GPIO for Brightness adjustment, duty cycle = period. */
428 MX6_PAD_GPIO1_IO08__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
429 };
430
setup_lcd(void)431 static int setup_lcd(void)
432 {
433 enable_lcdif_clock(LCDIF1_BASE_ADDR, 1);
434
435 imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
436
437 /* Reset the LCD */
438 gpio_request(IMX_GPIO_NR(5, 9), "lcd reset");
439 gpio_direction_output(IMX_GPIO_NR(5, 9) , 0);
440 udelay(500);
441 gpio_direction_output(IMX_GPIO_NR(5, 9) , 1);
442
443 /* Set Brightness to high */
444 gpio_request(IMX_GPIO_NR(1, 8), "backlight");
445 gpio_direction_output(IMX_GPIO_NR(1, 8) , 1);
446
447 return 0;
448 }
449 #else
setup_lcd(void)450 static inline int setup_lcd(void) { return 0; }
451 #endif
452
board_early_init_f(void)453 int board_early_init_f(void)
454 {
455 setup_iomux_uart();
456
457 return 0;
458 }
459
board_init(void)460 int board_init(void)
461 {
462 /* Address of boot parameters */
463 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
464
465 #ifdef CONFIG_FEC_MXC
466 setup_fec(CONFIG_FEC_ENET_DEV);
467 #endif
468
469 #ifdef CONFIG_USB_EHCI_MX6
470 #ifndef CONFIG_DM_USB
471 setup_usb();
472 #endif
473 #endif
474
475 #ifdef CONFIG_FSL_QSPI
476 board_qspi_init();
477 #endif
478
479 return 0;
480 }
481
482 #ifdef CONFIG_CMD_BMODE
483 static const struct boot_mode board_boot_modes[] = {
484 /* 4 bit bus width */
485 {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
486 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
487 {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
488 {NULL, 0},
489 };
490 #endif
491
board_late_init(void)492 int board_late_init(void)
493 {
494 #ifdef CONFIG_CMD_BMODE
495 add_board_boot_modes(board_boot_modes);
496 #endif
497
498 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
499 env_set("board_name", "EVK");
500
501 if (is_mx6ul_9x9_evk())
502 env_set("board_rev", "9X9");
503 else
504 env_set("board_rev", "14X14");
505 #endif
506
507 setup_lcd();
508
509 return 0;
510 }
511
checkboard(void)512 int checkboard(void)
513 {
514 if (is_mx6ul_9x9_evk())
515 puts("Board: MX6UL 9x9 EVK\n");
516 else
517 puts("Board: MX6UL 14x14 EVK\n");
518
519 return 0;
520 }
521
522 #ifdef CONFIG_SPL_BUILD
523 #include <linux/libfdt.h>
524 #include <spl.h>
525 #include <asm/arch/mx6-ddr.h>
526
527
528 static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
529 .grp_addds = 0x00000030,
530 .grp_ddrmode_ctl = 0x00020000,
531 .grp_b0ds = 0x00000030,
532 .grp_ctlds = 0x00000030,
533 .grp_b1ds = 0x00000030,
534 .grp_ddrpke = 0x00000000,
535 .grp_ddrmode = 0x00020000,
536 #ifdef CONFIG_TARGET_MX6UL_9X9_EVK
537 .grp_ddr_type = 0x00080000,
538 #else
539 .grp_ddr_type = 0x000c0000,
540 #endif
541 };
542
543 #ifdef CONFIG_TARGET_MX6UL_9X9_EVK
544 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
545 .dram_dqm0 = 0x00000030,
546 .dram_dqm1 = 0x00000030,
547 .dram_ras = 0x00000030,
548 .dram_cas = 0x00000030,
549 .dram_odt0 = 0x00000000,
550 .dram_odt1 = 0x00000000,
551 .dram_sdba2 = 0x00000000,
552 .dram_sdclk_0 = 0x00000030,
553 .dram_sdqs0 = 0x00003030,
554 .dram_sdqs1 = 0x00003030,
555 .dram_reset = 0x00000030,
556 };
557
558 static struct mx6_mmdc_calibration mx6_mmcd_calib = {
559 .p0_mpwldectrl0 = 0x00000000,
560 .p0_mpdgctrl0 = 0x20000000,
561 .p0_mprddlctl = 0x4040484f,
562 .p0_mpwrdlctl = 0x40405247,
563 .mpzqlp2ctl = 0x1b4700c7,
564 };
565
566 static struct mx6_lpddr2_cfg mem_ddr = {
567 .mem_speed = 800,
568 .density = 2,
569 .width = 16,
570 .banks = 4,
571 .rowaddr = 14,
572 .coladdr = 10,
573 .trcd_lp = 1500,
574 .trppb_lp = 1500,
575 .trpab_lp = 2000,
576 .trasmin = 4250,
577 };
578
579 struct mx6_ddr_sysinfo ddr_sysinfo = {
580 .dsize = 0,
581 .cs_density = 18,
582 .ncs = 1,
583 .cs1_mirror = 0,
584 .walat = 0,
585 .ralat = 5,
586 .mif3_mode = 3,
587 .bi_on = 1,
588 .rtt_wr = 0, /* LPDDR2 does not need rtt_wr rtt_nom */
589 .rtt_nom = 0,
590 .sde_to_rst = 0, /* LPDDR2 does not need this field */
591 .rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
592 .ddr_type = DDR_TYPE_LPDDR2,
593 .refsel = 0, /* Refresh cycles at 64KHz */
594 .refr = 3, /* 4 refresh commands per refresh cycle */
595 };
596
597 #else
598 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
599 .dram_dqm0 = 0x00000030,
600 .dram_dqm1 = 0x00000030,
601 .dram_ras = 0x00000030,
602 .dram_cas = 0x00000030,
603 .dram_odt0 = 0x00000030,
604 .dram_odt1 = 0x00000030,
605 .dram_sdba2 = 0x00000000,
606 .dram_sdclk_0 = 0x00000030,
607 .dram_sdqs0 = 0x00000030,
608 .dram_sdqs1 = 0x00000030,
609 .dram_reset = 0x00000030,
610 };
611
612 static struct mx6_mmdc_calibration mx6_mmcd_calib = {
613 .p0_mpwldectrl0 = 0x00000000,
614 .p0_mpdgctrl0 = 0x41570155,
615 .p0_mprddlctl = 0x4040474A,
616 .p0_mpwrdlctl = 0x40405550,
617 };
618
619 struct mx6_ddr_sysinfo ddr_sysinfo = {
620 .dsize = 0,
621 .cs_density = 20,
622 .ncs = 1,
623 .cs1_mirror = 0,
624 .rtt_wr = 2,
625 .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
626 .walat = 0, /* Write additional latency */
627 .ralat = 5, /* Read additional latency */
628 .mif3_mode = 3, /* Command prediction working mode */
629 .bi_on = 1, /* Bank interleaving enabled */
630 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
631 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
632 .ddr_type = DDR_TYPE_DDR3,
633 .refsel = 0, /* Refresh cycles at 64KHz */
634 .refr = 1, /* 2 refresh commands per refresh cycle */
635 };
636
637 static struct mx6_ddr3_cfg mem_ddr = {
638 .mem_speed = 800,
639 .density = 4,
640 .width = 16,
641 .banks = 8,
642 .rowaddr = 15,
643 .coladdr = 10,
644 .pagesz = 2,
645 .trcd = 1375,
646 .trcmin = 4875,
647 .trasmin = 3500,
648 };
649 #endif
650
ccgr_init(void)651 static void ccgr_init(void)
652 {
653 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
654
655 writel(0xFFFFFFFF, &ccm->CCGR0);
656 writel(0xFFFFFFFF, &ccm->CCGR1);
657 writel(0xFFFFFFFF, &ccm->CCGR2);
658 writel(0xFFFFFFFF, &ccm->CCGR3);
659 writel(0xFFFFFFFF, &ccm->CCGR4);
660 writel(0xFFFFFFFF, &ccm->CCGR5);
661 writel(0xFFFFFFFF, &ccm->CCGR6);
662 writel(0xFFFFFFFF, &ccm->CCGR7);
663 }
664
spl_dram_init(void)665 static void spl_dram_init(void)
666 {
667 mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
668 mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
669 }
670
board_init_f(ulong dummy)671 void board_init_f(ulong dummy)
672 {
673 ccgr_init();
674
675 /* setup AIPS and disable watchdog */
676 arch_cpu_init();
677
678 /* iomux and setup of i2c */
679 board_early_init_f();
680
681 /* setup GP timer */
682 timer_init();
683
684 /* UART clocks enabled and gd valid - init serial console */
685 preloader_console_init();
686
687 /* DDR initialization */
688 spl_dram_init();
689
690 /* Clear the BSS. */
691 memset(__bss_start, 0, __bss_end - __bss_start);
692
693 /* load/boot image from boot device */
694 board_init_r(NULL, 0);
695 }
696 #endif
697