1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2013 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <command.h>
8 #include <env.h>
9 #include <hwconfig.h>
10 #include <init.h>
11 #include <pci.h>
12 #include <i2c.h>
13 #include <asm/processor.h>
14 #include <asm/mmu.h>
15 #include <asm/cache.h>
16 #include <asm/immap_85xx.h>
17 #include <asm/fsl_pci.h>
18 #include <fsl_ddr_sdram.h>
19 #include <asm/io.h>
20 #include <asm/fsl_law.h>
21 #include <asm/fsl_lbc.h>
22 #include <asm/mp.h>
23 #include <miiphy.h>
24 #include <linux/libfdt.h>
25 #include <fdt_support.h>
26 #include <fsl_mdio.h>
27 #include <tsec.h>
28 #include <ioports.h>
29 #include <asm/fsl_serdes.h>
30 #include <netdev.h>
31
32 #define SYSCLK_64 64000000
33 #define SYSCLK_66 66666666
34
get_board_sys_clk(ulong dummy)35 unsigned long get_board_sys_clk(ulong dummy)
36 {
37 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
38 par_io_t *par_io = (par_io_t *) &(gur->qe_par_io);
39 unsigned int cpdat_val = 0;
40
41 /* Set-up up pin muxing based on board switch settings */
42 cpdat_val = par_io[1].cpdat;
43
44 /* Check switch setting for SYSCLK select (PB3) */
45 if (cpdat_val & 0x10000000)
46 return SYSCLK_64;
47 else
48 return SYSCLK_66;
49
50 return 0;
51 }
52
53 #ifdef CONFIG_QE
54
55 #define PCA_IOPORT_I2C_ADDR 0x23
56 #define PCA_IOPORT_OUTPUT_CMD 0x2
57 #define PCA_IOPORT_CFG_CMD 0x6
58
59 const qe_iop_conf_t qe_iop_conf_tab[] = {
60
61 #ifdef CONFIG_TWR_P1025
62 /* GPIO */
63 {1, 0, 1, 0, 0},
64 {1, 18, 1, 0, 0},
65
66 /* GPIO for switch options */
67 {1, 2, 2, 0, 0}, /* PROFIBUS_MODE_SEL */
68 {1, 3, 2, 0, 0}, /* SYS_CLK_SELECT */
69 {1, 29, 2, 0, 0}, /* LOCALBUS_QE_MUXSEL */
70 {1, 30, 2, 0, 0}, /* ETH_TDM_SEL */
71
72 /* QE_MUX_MDC */
73 {1, 19, 1, 0, 1}, /* QE_MUX_MDC */
74
75 /* QE_MUX_MDIO */
76 {1, 20, 3, 0, 1}, /* QE_MUX_MDIO */
77
78 /* UCC_1_MII */
79 {0, 23, 2, 0, 2}, /* CLK12 */
80 {0, 24, 2, 0, 1}, /* CLK9 */
81 {0, 7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0 */
82 {0, 9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1 */
83 {0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2 */
84 {0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */
85 {0, 6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0 */
86 {0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1 */
87 {0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */
88 {0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */
89 {0, 5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
90 {0, 13, 1, 0, 2}, /* ENET1_TX_ER */
91 {0, 4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B */
92 {0, 8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B */
93 {0, 17, 2, 0, 2}, /* ENET1_CRS */
94 {0, 16, 2, 0, 2}, /* ENET1_COL */
95
96 /* UCC_5_RMII */
97 {1, 11, 2, 0, 1}, /* CLK13 */
98 {1, 7, 1, 0, 2}, /* ENET5_TXD0_SER5_TXD0 */
99 {1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1 */
100 {1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0 */
101 {1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1 */
102 {1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B */
103 {1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B */
104 {1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B */
105
106 /* TDMA - clock option is configured in OS based on board setting */
107 {1, 23, 2, 0, 2}, /* TDMA_TXD */
108 {1, 25, 2, 0, 2}, /* TDMA_RXD */
109 {1, 26, 1, 0, 2}, /* TDMA_SYNC */
110 #endif
111
112 {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
113 };
114 #endif
115
board_early_init_f(void)116 int board_early_init_f(void)
117 {
118 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
119
120 setbits_be32(&gur->pmuxcr,
121 (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP));
122
123 /* SDHC_DAT[4:7] not exposed to pins (use as SPI) */
124 clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
125
126 return 0;
127 }
128
checkboard(void)129 int checkboard(void)
130 {
131 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
132 u8 boot_status;
133
134 printf("Board: %s\n", CONFIG_BOARDNAME);
135
136 boot_status = ((gur->porbmsr) >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;
137 puts("rom_loc: ");
138 if (boot_status == PORBMSR_ROMLOC_NOR)
139 puts("nor flash");
140 else if (boot_status == PORBMSR_ROMLOC_SDHC)
141 puts("sd");
142 else
143 puts("unknown");
144 puts("\n");
145
146 return 0;
147 }
148
149 #ifdef CONFIG_PCI
pci_init_board(void)150 void pci_init_board(void)
151 {
152 fsl_pcie_init_board(0);
153 }
154 #endif
155
board_early_init_r(void)156 int board_early_init_r(void)
157 {
158 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
159 int flash_esel = find_tlb_idx((void *)flashbase, 1);
160
161 /*
162 * Remap Boot flash region to caching-inhibited
163 * so that flash can be erased properly.
164 */
165
166 /* Flush d-cache and invalidate i-cache of any FLASH data */
167 flush_dcache();
168 invalidate_icache();
169
170 if (flash_esel == -1) {
171 /* very unlikely unless something is messed up */
172 puts("Error: Could not find TLB for FLASH BASE\n");
173 flash_esel = 2; /* give our best effort to continue */
174 } else {
175 /* invalidate existing TLB entry for flash */
176 disable_tlb(flash_esel);
177 }
178
179 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
180 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
181 0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
182 return 0;
183 }
184
board_eth_init(bd_t * bis)185 int board_eth_init(bd_t *bis)
186 {
187 struct fsl_pq_mdio_info mdio_info;
188 struct tsec_info_struct tsec_info[4];
189 ccsr_gur_t *gur __attribute__((unused)) =
190 (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
191 int num = 0;
192
193 #ifdef CONFIG_TSEC1
194 SET_STD_TSEC_INFO(tsec_info[num], 1);
195 num++;
196 #endif
197 #ifdef CONFIG_TSEC2
198 SET_STD_TSEC_INFO(tsec_info[num], 2);
199 if (is_serdes_configured(SGMII_TSEC2)) {
200 printf("eTSEC2 is in sgmii mode.\n");
201 tsec_info[num].flags |= TSEC_SGMII;
202 }
203 num++;
204 #endif
205 #ifdef CONFIG_TSEC3
206 SET_STD_TSEC_INFO(tsec_info[num], 3);
207 num++;
208 #endif
209
210 if (!num) {
211 printf("No TSECs initialized\n");
212 return 0;
213 }
214
215 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
216 mdio_info.name = DEFAULT_MII_NAME;
217
218 fsl_pq_mdio_init(bis, &mdio_info);
219
220 tsec_eth_init(bis, tsec_info, num);
221
222 #if defined(CONFIG_UEC_ETH)
223 /* QE0 and QE3 need to be exposed for UCC1
224 * and UCC5 Eth mode (in PMUXCR register).
225 * Currently QE/LBC muxed pins assumed to be
226 * LBC for U-Boot and PMUXCR updated by OS if required */
227
228 uec_standard_init(bis);
229 #endif
230
231 return pci_eth_init(bis);
232 }
233
234 #if defined(CONFIG_QE)
fdt_board_fixup_qe_pins(void * blob)235 static void fdt_board_fixup_qe_pins(void *blob)
236 {
237 int node;
238
239 if (!hwconfig("qe")) {
240 /* For QE and eLBC pins multiplexing,
241 * When don't use QE function, remove
242 * qe node from dt blob.
243 */
244 node = fdt_path_offset(blob, "/qe");
245 if (node >= 0)
246 fdt_del_node(blob, node);
247 } else {
248 /* For TWR Peripheral Modules - TWR-SER2
249 * board only can support Signal Port MII,
250 * so delete one UEC node when use MII port.
251 */
252 if (hwconfig("mii"))
253 node = fdt_path_offset(blob, "/qe/ucc@2400");
254 else
255 node = fdt_path_offset(blob, "/qe/ucc@2000");
256 if (node >= 0)
257 fdt_del_node(blob, node);
258 }
259
260 return;
261 }
262 #endif
263
264 #ifdef CONFIG_OF_BOARD_SETUP
ft_board_setup(void * blob,bd_t * bd)265 int ft_board_setup(void *blob, bd_t *bd)
266 {
267 phys_addr_t base;
268 phys_size_t size;
269
270 ft_cpu_setup(blob, bd);
271
272 base = env_get_bootm_low();
273 size = env_get_bootm_size();
274
275 fdt_fixup_memory(blob, (u64)base, (u64)size);
276
277 FT_FSL_PCI_SETUP;
278
279 #ifdef CONFIG_QE
280 do_fixup_by_compat(blob, "fsl,qe", "status", "okay",
281 sizeof("okay"), 0);
282 #endif
283 #if defined(CONFIG_TWR_P1025)
284 fdt_board_fixup_qe_pins(blob);
285 #endif
286 fsl_fdt_fixup_dr_usb(blob, bd);
287
288 return 0;
289 }
290 #endif
291