1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2013 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <command.h>
8 #include <env.h>
9 #include <i2c.h>
10 #include <init.h>
11 #include <netdev.h>
12 #include <linux/compiler.h>
13 #include <asm/mmu.h>
14 #include <asm/processor.h>
15 #include <asm/cache.h>
16 #include <asm/immap_85xx.h>
17 #include <asm/fsl_law.h>
18 #include <asm/fsl_serdes.h>
19 #include <asm/fsl_liodn.h>
20 #include <fm_eth.h>
21 #include <hwconfig.h>
22
23 #include "../common/sleep.h"
24 #include "../common/qixis.h"
25 #include "t1040qds.h"
26 #include "t1040qds_qixis.h"
27
28 DECLARE_GLOBAL_DATA_PTR;
29
checkboard(void)30 int checkboard(void)
31 {
32 char buf[64];
33 u8 sw;
34 struct cpu_type *cpu = gd->arch.cpu;
35 static const char *const freq[] = {"100", "125", "156.25", "161.13",
36 "122.88", "122.88", "122.88"};
37 int clock;
38
39 printf("Board: %sQDS, ", cpu->name);
40 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
41 QIXIS_READ(id), QIXIS_READ(arch));
42
43 sw = QIXIS_READ(brdcfg[0]);
44 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
45
46 if (sw < 0x8)
47 printf("vBank: %d\n", sw);
48 else if (sw == 0x8)
49 puts("PromJet\n");
50 else if (sw == 0x9)
51 puts("NAND\n");
52 else if (sw == 0x15)
53 printf("IFCCard\n");
54 else
55 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
56
57 printf("FPGA: v%d (%s), build %d",
58 (int)QIXIS_READ(scver), qixis_read_tag(buf),
59 (int)qixis_read_minor());
60 /* the timestamp string contains "\n" at the end */
61 printf(" on %s", qixis_read_time(buf));
62
63 /*
64 * Display the actual SERDES reference clocks as configured by the
65 * dip switches on the board. Note that the SWx registers could
66 * technically be set to force the reference clocks to match the
67 * values that the SERDES expects (or vice versa). For now, however,
68 * we just display both values and hope the user notices when they
69 * don't match.
70 */
71 puts("SERDES Reference: ");
72 sw = QIXIS_READ(brdcfg[2]);
73 clock = (sw >> 6) & 3;
74 printf("Clock1=%sMHz ", freq[clock]);
75 clock = (sw >> 4) & 3;
76 printf("Clock2=%sMHz\n", freq[clock]);
77
78 return 0;
79 }
80
select_i2c_ch_pca9547(u8 ch)81 int select_i2c_ch_pca9547(u8 ch)
82 {
83 int ret;
84
85 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
86 if (ret) {
87 puts("PCA: failed to select proper channel\n");
88 return ret;
89 }
90
91 return 0;
92 }
93
qe_board_setup(void)94 static void qe_board_setup(void)
95 {
96 u8 brdcfg15, brdcfg9;
97
98 if (hwconfig("qe") && hwconfig("tdm")) {
99 brdcfg15 = QIXIS_READ(brdcfg[15]);
100 /*
101 * TDMRiser uses QE-TDM
102 * Route QE_TDM signals to TDM Riser slot
103 */
104 QIXIS_WRITE(brdcfg[15], brdcfg15 | 7);
105 } else if (hwconfig("qe") && hwconfig("uart")) {
106 brdcfg15 = QIXIS_READ(brdcfg[15]);
107 brdcfg9 = QIXIS_READ(brdcfg[9]);
108 /*
109 * Route QE_TDM signals to UCC
110 * ProfiBus controlled by UCC3
111 */
112 brdcfg15 &= 0xfc;
113 QIXIS_WRITE(brdcfg[15], brdcfg15 | 2);
114 QIXIS_WRITE(brdcfg[9], brdcfg9 | 4);
115 }
116 }
117
board_early_init_f(void)118 int board_early_init_f(void)
119 {
120 #if defined(CONFIG_DEEP_SLEEP)
121 if (is_warm_boot())
122 fsl_dp_disable_console();
123 #endif
124
125 return 0;
126 }
127
board_early_init_r(void)128 int board_early_init_r(void)
129 {
130 #ifdef CONFIG_SYS_FLASH_BASE
131 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
132 int flash_esel = find_tlb_idx((void *)flashbase, 1);
133
134 /*
135 * Remap Boot flash + PROMJET region to caching-inhibited
136 * so that flash can be erased properly.
137 */
138
139 /* Flush d-cache and invalidate i-cache of any FLASH data */
140 flush_dcache();
141 invalidate_icache();
142
143 if (flash_esel == -1) {
144 /* very unlikely unless something is messed up */
145 puts("Error: Could not find TLB for FLASH BASE\n");
146 flash_esel = 2; /* give our best effort to continue */
147 } else {
148 /* invalidate existing TLB entry for flash + promjet */
149 disable_tlb(flash_esel);
150 }
151
152 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
153 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
154 0, flash_esel, BOOKE_PAGESZ_256M, 1);
155 #endif
156 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
157
158 return 0;
159 }
160
get_board_sys_clk(void)161 unsigned long get_board_sys_clk(void)
162 {
163 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
164
165 switch (sysclk_conf & 0x0F) {
166 case QIXIS_SYSCLK_64:
167 return 64000000;
168 case QIXIS_SYSCLK_83:
169 return 83333333;
170 case QIXIS_SYSCLK_100:
171 return 100000000;
172 case QIXIS_SYSCLK_125:
173 return 125000000;
174 case QIXIS_SYSCLK_133:
175 return 133333333;
176 case QIXIS_SYSCLK_150:
177 return 150000000;
178 case QIXIS_SYSCLK_160:
179 return 160000000;
180 case QIXIS_SYSCLK_166:
181 return 166666666;
182 }
183 return 66666666;
184 }
185
get_board_ddr_clk(void)186 unsigned long get_board_ddr_clk(void)
187 {
188 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
189
190 switch ((ddrclk_conf & 0x30) >> 4) {
191 case QIXIS_DDRCLK_100:
192 return 100000000;
193 case QIXIS_DDRCLK_125:
194 return 125000000;
195 case QIXIS_DDRCLK_133:
196 return 133333333;
197 }
198 return 66666666;
199 }
200
201 #define NUM_SRDS_BANKS 2
misc_init_r(void)202 int misc_init_r(void)
203 {
204 u8 sw;
205 serdes_corenet_t *srds_regs =
206 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
207 u32 actual[NUM_SRDS_BANKS] = { 0 };
208 int i;
209
210 sw = QIXIS_READ(brdcfg[2]);
211 for (i = 0; i < NUM_SRDS_BANKS; i++) {
212 unsigned int clock = (sw >> (6 - 2 * i)) & 3;
213 switch (clock) {
214 case 0:
215 actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
216 break;
217 case 1:
218 actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
219 break;
220 case 2:
221 actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
222 break;
223 }
224 }
225
226 puts("SerDes1");
227 for (i = 0; i < NUM_SRDS_BANKS; i++) {
228 u32 pllcr0 = srds_regs->bank[i].pllcr0;
229 u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
230 if (expected != actual[i]) {
231 printf("expects ref clk%d %sMHz, but actual is %sMHz\n",
232 i + 1, serdes_clock_to_string(expected),
233 serdes_clock_to_string(actual[i]));
234 }
235 }
236
237 qe_board_setup();
238
239 return 0;
240 }
241
ft_board_setup(void * blob,bd_t * bd)242 int ft_board_setup(void *blob, bd_t *bd)
243 {
244 phys_addr_t base;
245 phys_size_t size;
246
247 ft_cpu_setup(blob, bd);
248
249 base = env_get_bootm_low();
250 size = env_get_bootm_size();
251
252 fdt_fixup_memory(blob, (u64)base, (u64)size);
253
254 #ifdef CONFIG_PCI
255 pci_of_setup(blob, bd);
256 #endif
257
258 fdt_fixup_liodn(blob);
259
260 #ifdef CONFIG_HAS_FSL_DR_USB
261 fsl_fdt_fixup_dr_usb(blob, bd);
262 #endif
263
264 #ifdef CONFIG_SYS_DPAA_FMAN
265 fdt_fixup_fman_ethernet(blob);
266 fdt_fixup_board_enet(blob);
267 #endif
268
269 return 0;
270 }
271
qixis_dump_switch(void)272 void qixis_dump_switch(void)
273 {
274 int i, nr_of_cfgsw;
275
276 QIXIS_WRITE(cms[0], 0x00);
277 nr_of_cfgsw = QIXIS_READ(cms[1]);
278
279 puts("DIP switch settings dump:\n");
280 for (i = 1; i <= nr_of_cfgsw; i++) {
281 QIXIS_WRITE(cms[0], i);
282 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
283 }
284 }
285
board_need_mem_reset(void)286 int board_need_mem_reset(void)
287 {
288 return 1;
289 }
290