1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2014 Gateworks Corporation
4 * Author: Tim Harvey <tharvey@gateworks.com>
5 */
6
7 #include <common.h>
8 #include <env.h>
9 #include <asm/io.h>
10 #include <asm/arch/crm_regs.h>
11 #include <asm/arch/mx6-ddr.h>
12 #include <asm/arch/mx6-pins.h>
13 #include <asm/arch/sys_proto.h>
14 #include <asm/mach-imx/boot_mode.h>
15 #include <asm/mach-imx/iomux-v3.h>
16 #include <asm/mach-imx/mxc_i2c.h>
17 #include <env.h>
18 #include <i2c.h>
19 #include <spl.h>
20
21 #include "gsc.h"
22 #include "common.h"
23
24 #define RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */
25 #define GSC_EEPROM_DDR_SIZE 0x2B /* enum (512,1024,2048) MB */
26 #define GSC_EEPROM_DDR_WIDTH 0x2D /* enum (32,64) bit */
27
28 /* configure MX6Q/DUAL mmdc DDR io registers */
29 struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
30 /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
31 .dram_sdclk_0 = 0x00020030,
32 .dram_sdclk_1 = 0x00020030,
33 .dram_cas = 0x00020030,
34 .dram_ras = 0x00020030,
35 .dram_reset = 0x00020030,
36 /* SDCKE[0:1]: 100k pull-up */
37 .dram_sdcke0 = 0x00003000,
38 .dram_sdcke1 = 0x00003000,
39 /* SDBA2: pull-up disabled */
40 .dram_sdba2 = 0x00000000,
41 /* SDODT[0:1]: 100k pull-up, 40 ohm */
42 .dram_sdodt0 = 0x00003030,
43 .dram_sdodt1 = 0x00003030,
44 /* SDQS[0:7]: Differential input, 40 ohm */
45 .dram_sdqs0 = 0x00000030,
46 .dram_sdqs1 = 0x00000030,
47 .dram_sdqs2 = 0x00000030,
48 .dram_sdqs3 = 0x00000030,
49 .dram_sdqs4 = 0x00000030,
50 .dram_sdqs5 = 0x00000030,
51 .dram_sdqs6 = 0x00000030,
52 .dram_sdqs7 = 0x00000030,
53
54 /* DQM[0:7]: Differential input, 40 ohm */
55 .dram_dqm0 = 0x00020030,
56 .dram_dqm1 = 0x00020030,
57 .dram_dqm2 = 0x00020030,
58 .dram_dqm3 = 0x00020030,
59 .dram_dqm4 = 0x00020030,
60 .dram_dqm5 = 0x00020030,
61 .dram_dqm6 = 0x00020030,
62 .dram_dqm7 = 0x00020030,
63 };
64
65 /* configure MX6Q/DUAL mmdc GRP io registers */
66 struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
67 /* DDR3 */
68 .grp_ddr_type = 0x000c0000,
69 .grp_ddrmode_ctl = 0x00020000,
70 /* disable DDR pullups */
71 .grp_ddrpke = 0x00000000,
72 /* ADDR[00:16], SDBA[0:1]: 40 ohm */
73 .grp_addds = 0x00000030,
74 /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
75 .grp_ctlds = 0x00000030,
76 /* DATA[00:63]: Differential input, 40 ohm */
77 .grp_ddrmode = 0x00020000,
78 .grp_b0ds = 0x00000030,
79 .grp_b1ds = 0x00000030,
80 .grp_b2ds = 0x00000030,
81 .grp_b3ds = 0x00000030,
82 .grp_b4ds = 0x00000030,
83 .grp_b5ds = 0x00000030,
84 .grp_b6ds = 0x00000030,
85 .grp_b7ds = 0x00000030,
86 };
87
88 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
89 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
90 /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
91 .dram_sdclk_0 = 0x00020030,
92 .dram_sdclk_1 = 0x00020030,
93 .dram_cas = 0x00020030,
94 .dram_ras = 0x00020030,
95 .dram_reset = 0x00020030,
96 /* SDCKE[0:1]: 100k pull-up */
97 .dram_sdcke0 = 0x00003000,
98 .dram_sdcke1 = 0x00003000,
99 /* SDBA2: pull-up disabled */
100 .dram_sdba2 = 0x00000000,
101 /* SDODT[0:1]: 100k pull-up, 40 ohm */
102 .dram_sdodt0 = 0x00003030,
103 .dram_sdodt1 = 0x00003030,
104 /* SDQS[0:7]: Differential input, 40 ohm */
105 .dram_sdqs0 = 0x00000030,
106 .dram_sdqs1 = 0x00000030,
107 .dram_sdqs2 = 0x00000030,
108 .dram_sdqs3 = 0x00000030,
109 .dram_sdqs4 = 0x00000030,
110 .dram_sdqs5 = 0x00000030,
111 .dram_sdqs6 = 0x00000030,
112 .dram_sdqs7 = 0x00000030,
113
114 /* DQM[0:7]: Differential input, 40 ohm */
115 .dram_dqm0 = 0x00020030,
116 .dram_dqm1 = 0x00020030,
117 .dram_dqm2 = 0x00020030,
118 .dram_dqm3 = 0x00020030,
119 .dram_dqm4 = 0x00020030,
120 .dram_dqm5 = 0x00020030,
121 .dram_dqm6 = 0x00020030,
122 .dram_dqm7 = 0x00020030,
123 };
124
125 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
126 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
127 /* DDR3 */
128 .grp_ddr_type = 0x000c0000,
129 /* SDQS[0:7]: Differential input, 40 ohm */
130 .grp_ddrmode_ctl = 0x00020000,
131 /* disable DDR pullups */
132 .grp_ddrpke = 0x00000000,
133 /* ADDR[00:16], SDBA[0:1]: 40 ohm */
134 .grp_addds = 0x00000030,
135 /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
136 .grp_ctlds = 0x00000030,
137 /* DATA[00:63]: Differential input, 40 ohm */
138 .grp_ddrmode = 0x00020000,
139 .grp_b0ds = 0x00000030,
140 .grp_b1ds = 0x00000030,
141 .grp_b2ds = 0x00000030,
142 .grp_b3ds = 0x00000030,
143 .grp_b4ds = 0x00000030,
144 .grp_b5ds = 0x00000030,
145 .grp_b6ds = 0x00000030,
146 .grp_b7ds = 0x00000030,
147 };
148
149 /* MT41K64M16JT-125 (1Gb density) */
150 static struct mx6_ddr3_cfg mt41k64m16jt_125 = {
151 .mem_speed = 1600,
152 .density = 1,
153 .width = 16,
154 .banks = 8,
155 .rowaddr = 13,
156 .coladdr = 10,
157 .pagesz = 2,
158 .trcd = 1375,
159 .trcmin = 4875,
160 .trasmin = 3500,
161 };
162
163 /* MT41K128M16JT-125 (2Gb density) */
164 static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
165 .mem_speed = 1600,
166 .density = 2,
167 .width = 16,
168 .banks = 8,
169 .rowaddr = 14,
170 .coladdr = 10,
171 .pagesz = 2,
172 .trcd = 1375,
173 .trcmin = 4875,
174 .trasmin = 3500,
175 };
176
177 /* MT41K256M16HA-125 (4Gb density) */
178 static struct mx6_ddr3_cfg mt41k256m16ha_125 = {
179 .mem_speed = 1600,
180 .density = 4,
181 .width = 16,
182 .banks = 8,
183 .rowaddr = 15,
184 .coladdr = 10,
185 .pagesz = 2,
186 .trcd = 1375,
187 .trcmin = 4875,
188 .trasmin = 3500,
189 };
190
191 /* MT41K512M16HA-125 (8Gb density) */
192 static struct mx6_ddr3_cfg mt41k512m16ha_125 = {
193 .mem_speed = 1600,
194 .density = 8,
195 .width = 16,
196 .banks = 8,
197 .rowaddr = 16,
198 .coladdr = 10,
199 .pagesz = 2,
200 .trcd = 1375,
201 .trcmin = 4875,
202 .trasmin = 3500,
203 };
204
205 /*
206 * calibration - these are the various CPU/DDR3 combinations we support
207 */
208 static struct mx6_mmdc_calibration mx6sdl_64x16_mmdc_calib = {
209 /* write leveling calibration determine */
210 .p0_mpwldectrl0 = 0x004C004E,
211 .p0_mpwldectrl1 = 0x00440044,
212 /* Read DQS Gating calibration */
213 .p0_mpdgctrl0 = 0x42440247,
214 .p0_mpdgctrl1 = 0x02310232,
215 /* Read Calibration: DQS delay relative to DQ read access */
216 .p0_mprddlctl = 0x45424746,
217 /* Write Calibration: DQ/DM delay relative to DQS write access */
218 .p0_mpwrdlctl = 0x33382C31,
219 };
220
221 /* TODO: update with calibrated values */
222 static struct mx6_mmdc_calibration mx6dq_64x64_mmdc_calib = {
223 /* write leveling calibration determine */
224 .p0_mpwldectrl0 = 0x00190017,
225 .p0_mpwldectrl1 = 0x00140026,
226 .p1_mpwldectrl0 = 0x0021001C,
227 .p1_mpwldectrl1 = 0x0011001D,
228 /* Read DQS Gating calibration */
229 .p0_mpdgctrl0 = 0x43380347,
230 .p0_mpdgctrl1 = 0x433C034D,
231 .p1_mpdgctrl0 = 0x032C0324,
232 .p1_mpdgctrl1 = 0x03310232,
233 /* Read Calibration: DQS delay relative to DQ read access */
234 .p0_mprddlctl = 0x3C313539,
235 .p1_mprddlctl = 0x37343141,
236 /* Write Calibration: DQ/DM delay relative to DQS write access */
237 .p0_mpwrdlctl = 0x36393C39,
238 .p1_mpwrdlctl = 0x42344438,
239 };
240
241 /* TODO: update with calibrated values */
242 static struct mx6_mmdc_calibration mx6sdl_64x64_mmdc_calib = {
243 /* write leveling calibration determine */
244 .p0_mpwldectrl0 = 0x003C003C,
245 .p0_mpwldectrl1 = 0x001F002A,
246 .p1_mpwldectrl0 = 0x00330038,
247 .p1_mpwldectrl1 = 0x0022003F,
248 /* Read DQS Gating calibration */
249 .p0_mpdgctrl0 = 0x42410244,
250 .p0_mpdgctrl1 = 0x4234023A,
251 .p1_mpdgctrl0 = 0x022D022D,
252 .p1_mpdgctrl1 = 0x021C0228,
253 /* Read Calibration: DQS delay relative to DQ read access */
254 .p0_mprddlctl = 0x484A4C4B,
255 .p1_mprddlctl = 0x4B4D4E4B,
256 /* Write Calibration: DQ/DM delay relative to DQS write access */
257 .p0_mpwrdlctl = 0x33342B32,
258 .p1_mpwrdlctl = 0x3933332B,
259 };
260
261 static struct mx6_mmdc_calibration mx6dq_256x16_mmdc_calib = {
262 /* write leveling calibration determine */
263 .p0_mpwldectrl0 = 0x001B0016,
264 .p0_mpwldectrl1 = 0x000C000E,
265 /* Read DQS Gating calibration */
266 .p0_mpdgctrl0 = 0x4324033A,
267 .p0_mpdgctrl1 = 0x00000000,
268 /* Read Calibration: DQS delay relative to DQ read access */
269 .p0_mprddlctl = 0x40403438,
270 /* Write Calibration: DQ/DM delay relative to DQS write access */
271 .p0_mpwrdlctl = 0x40403D36,
272 };
273
274 static struct mx6_mmdc_calibration mx6sdl_256x16_mmdc_calib = {
275 /* write leveling calibration determine */
276 .p0_mpwldectrl0 = 0x00420043,
277 .p0_mpwldectrl1 = 0x0016001A,
278 /* Read DQS Gating calibration */
279 .p0_mpdgctrl0 = 0x4238023B,
280 .p0_mpdgctrl1 = 0x00000000,
281 /* Read Calibration: DQS delay relative to DQ read access */
282 .p0_mprddlctl = 0x40404849,
283 /* Write Calibration: DQ/DM delay relative to DQS write access */
284 .p0_mpwrdlctl = 0x40402E2F,
285 };
286
287 static struct mx6_mmdc_calibration mx6dq_128x32_mmdc_calib = {
288 /* write leveling calibration determine */
289 .p0_mpwldectrl0 = 0x00190017,
290 .p0_mpwldectrl1 = 0x00140026,
291 /* Read DQS Gating calibration */
292 .p0_mpdgctrl0 = 0x43380347,
293 .p0_mpdgctrl1 = 0x433C034D,
294 /* Read Calibration: DQS delay relative to DQ read access */
295 .p0_mprddlctl = 0x3C313539,
296 /* Write Calibration: DQ/DM delay relative to DQS write access */
297 .p0_mpwrdlctl = 0x36393C39,
298 };
299
300 static struct mx6_mmdc_calibration mx6sdl_128x32_mmdc_calib = {
301 /* write leveling calibration determine */
302 .p0_mpwldectrl0 = 0x003C003C,
303 .p0_mpwldectrl1 = 0x001F002A,
304 /* Read DQS Gating calibration */
305 .p0_mpdgctrl0 = 0x42410244,
306 .p0_mpdgctrl1 = 0x4234023A,
307 /* Read Calibration: DQS delay relative to DQ read access */
308 .p0_mprddlctl = 0x484A4C4B,
309 /* Write Calibration: DQ/DM delay relative to DQS write access */
310 .p0_mpwrdlctl = 0x33342B32,
311 };
312
313 static struct mx6_mmdc_calibration mx6dq_128x64_mmdc_calib = {
314 /* write leveling calibration determine */
315 .p0_mpwldectrl0 = 0x00190017,
316 .p0_mpwldectrl1 = 0x00140026,
317 .p1_mpwldectrl0 = 0x0021001C,
318 .p1_mpwldectrl1 = 0x0011001D,
319 /* Read DQS Gating calibration */
320 .p0_mpdgctrl0 = 0x43380347,
321 .p0_mpdgctrl1 = 0x433C034D,
322 .p1_mpdgctrl0 = 0x032C0324,
323 .p1_mpdgctrl1 = 0x03310232,
324 /* Read Calibration: DQS delay relative to DQ read access */
325 .p0_mprddlctl = 0x3C313539,
326 .p1_mprddlctl = 0x37343141,
327 /* Write Calibration: DQ/DM delay relative to DQS write access */
328 .p0_mpwrdlctl = 0x36393C39,
329 .p1_mpwrdlctl = 0x42344438,
330 };
331
332 static struct mx6_mmdc_calibration mx6sdl_128x64_mmdc_calib = {
333 /* write leveling calibration determine */
334 .p0_mpwldectrl0 = 0x003C003C,
335 .p0_mpwldectrl1 = 0x001F002A,
336 .p1_mpwldectrl0 = 0x00330038,
337 .p1_mpwldectrl1 = 0x0022003F,
338 /* Read DQS Gating calibration */
339 .p0_mpdgctrl0 = 0x42410244,
340 .p0_mpdgctrl1 = 0x4234023A,
341 .p1_mpdgctrl0 = 0x022D022D,
342 .p1_mpdgctrl1 = 0x021C0228,
343 /* Read Calibration: DQS delay relative to DQ read access */
344 .p0_mprddlctl = 0x484A4C4B,
345 .p1_mprddlctl = 0x4B4D4E4B,
346 /* Write Calibration: DQ/DM delay relative to DQS write access */
347 .p0_mpwrdlctl = 0x33342B32,
348 .p1_mpwrdlctl = 0x3933332B,
349 };
350
351 static struct mx6_mmdc_calibration mx6dq_256x32_mmdc_calib = {
352 /* write leveling calibration determine */
353 .p0_mpwldectrl0 = 0x001E001A,
354 .p0_mpwldectrl1 = 0x0026001F,
355 /* Read DQS Gating calibration */
356 .p0_mpdgctrl0 = 0x43370349,
357 .p0_mpdgctrl1 = 0x032D0327,
358 /* Read Calibration: DQS delay relative to DQ read access */
359 .p0_mprddlctl = 0x3D303639,
360 /* Write Calibration: DQ/DM delay relative to DQS write access */
361 .p0_mpwrdlctl = 0x32363934,
362 };
363
364 static struct mx6_mmdc_calibration mx6sdl_256x32_mmdc_calib = {
365 /* write leveling calibration determine */
366 .p0_mpwldectrl0 = 0X00480047,
367 .p0_mpwldectrl1 = 0X003D003F,
368 /* Read DQS Gating calibration */
369 .p0_mpdgctrl0 = 0X423E0241,
370 .p0_mpdgctrl1 = 0X022B022C,
371 /* Read Calibration: DQS delay relative to DQ read access */
372 .p0_mprddlctl = 0X49454A4A,
373 /* Write Calibration: DQ/DM delay relative to DQS write access */
374 .p0_mpwrdlctl = 0X2E372C32,
375 };
376
377 static struct mx6_mmdc_calibration mx6dq_256x64_mmdc_calib = {
378 /* write leveling calibration determine */
379 .p0_mpwldectrl0 = 0X00220021,
380 .p0_mpwldectrl1 = 0X00200030,
381 .p1_mpwldectrl0 = 0X002D0027,
382 .p1_mpwldectrl1 = 0X00150026,
383 /* Read DQS Gating calibration */
384 .p0_mpdgctrl0 = 0x43330342,
385 .p0_mpdgctrl1 = 0x0339034A,
386 .p1_mpdgctrl0 = 0x032F0325,
387 .p1_mpdgctrl1 = 0x032F022E,
388 /* Read Calibration: DQS delay relative to DQ read access */
389 .p0_mprddlctl = 0X3A2E3437,
390 .p1_mprddlctl = 0X35312F3F,
391 /* Write Calibration: DQ/DM delay relative to DQS write access */
392 .p0_mpwrdlctl = 0X33363B37,
393 .p1_mpwrdlctl = 0X40304239,
394 };
395
396 static struct mx6_mmdc_calibration mx6sdl_256x64_mmdc_calib = {
397 /* write leveling calibration determine */
398 .p0_mpwldectrl0 = 0x0048004A,
399 .p0_mpwldectrl1 = 0x003F004A,
400 .p1_mpwldectrl0 = 0x001E0028,
401 .p1_mpwldectrl1 = 0x002C0043,
402 /* Read DQS Gating calibration */
403 .p0_mpdgctrl0 = 0x02250219,
404 .p0_mpdgctrl1 = 0x01790202,
405 .p1_mpdgctrl0 = 0x02080208,
406 .p1_mpdgctrl1 = 0x016C0175,
407 /* Read Calibration: DQS delay relative to DQ read access */
408 .p0_mprddlctl = 0x4A4C4D4C,
409 .p1_mprddlctl = 0x494C4A48,
410 /* Write Calibration: DQ/DM delay relative to DQS write access */
411 .p0_mpwrdlctl = 0x403F3437,
412 .p1_mpwrdlctl = 0x383A3930,
413 };
414
415 static struct mx6_mmdc_calibration mx6sdl_256x64x2_mmdc_calib = {
416 /* write leveling calibration determine */
417 .p0_mpwldectrl0 = 0x001F003F,
418 .p0_mpwldectrl1 = 0x001F001F,
419 .p1_mpwldectrl0 = 0x001F004E,
420 .p1_mpwldectrl1 = 0x0059001F,
421 /* Read DQS Gating calibration */
422 .p0_mpdgctrl0 = 0x42220225,
423 .p0_mpdgctrl1 = 0x0213021F,
424 .p1_mpdgctrl0 = 0x022C0242,
425 .p1_mpdgctrl1 = 0x022C0244,
426 /* Read Calibration: DQS delay relative to DQ read access */
427 .p0_mprddlctl = 0x474A4C4A,
428 .p1_mprddlctl = 0x48494C45,
429 /* Write Calibration: DQ/DM delay relative to DQS write access */
430 .p0_mpwrdlctl = 0x3F3F3F36,
431 .p1_mpwrdlctl = 0x3F36363F,
432 };
433
434 static struct mx6_mmdc_calibration mx6sdl_128x64x2_mmdc_calib = {
435 /* write leveling calibration determine */
436 .p0_mpwldectrl0 = 0x001F003F,
437 .p0_mpwldectrl1 = 0x001F001F,
438 .p1_mpwldectrl0 = 0x001F004E,
439 .p1_mpwldectrl1 = 0x0059001F,
440 /* Read DQS Gating calibration */
441 .p0_mpdgctrl0 = 0x42220225,
442 .p0_mpdgctrl1 = 0x0213021F,
443 .p1_mpdgctrl0 = 0x022C0242,
444 .p1_mpdgctrl1 = 0x022C0244,
445 /* Read Calibration: DQS delay relative to DQ read access */
446 .p0_mprddlctl = 0x474A4C4A,
447 .p1_mprddlctl = 0x48494C45,
448 /* Write Calibration: DQ/DM delay relative to DQS write access */
449 .p0_mpwrdlctl = 0x3F3F3F36,
450 .p1_mpwrdlctl = 0x3F36363F,
451 };
452
453 static struct mx6_mmdc_calibration mx6dq_512x32_mmdc_calib = {
454 /* write leveling calibration determine */
455 .p0_mpwldectrl0 = 0x002A0025,
456 .p0_mpwldectrl1 = 0x003A002A,
457 /* Read DQS Gating calibration */
458 .p0_mpdgctrl0 = 0x43430356,
459 .p0_mpdgctrl1 = 0x033C0335,
460 /* Read Calibration: DQS delay relative to DQ read access */
461 .p0_mprddlctl = 0x4B373F42,
462 /* Write Calibration: DQ/DM delay relative to DQS write access */
463 .p0_mpwrdlctl = 0x303E3C36,
464 };
465
466 static struct mx6_mmdc_calibration mx6dq_512x64_mmdc_calib = {
467 /* write leveling calibration determine */
468 .p0_mpwldectrl0 = 0x00230020,
469 .p0_mpwldectrl1 = 0x002F002A,
470 .p1_mpwldectrl0 = 0x001D0027,
471 .p1_mpwldectrl1 = 0x00100023,
472 /* Read DQS Gating calibration */
473 .p0_mpdgctrl0 = 0x03250339,
474 .p0_mpdgctrl1 = 0x031C0316,
475 .p1_mpdgctrl0 = 0x03210331,
476 .p1_mpdgctrl1 = 0x031C025A,
477 /* Read Calibration: DQS delay relative to DQ read access */
478 .p0_mprddlctl = 0x40373C40,
479 .p1_mprddlctl = 0x3A373646,
480 /* Write Calibration: DQ/DM delay relative to DQS write access */
481 .p0_mpwrdlctl = 0x2E353933,
482 .p1_mpwrdlctl = 0x3C2F3F35,
483 };
484
spl_dram_init(int width,int size_mb,int board_model)485 static void spl_dram_init(int width, int size_mb, int board_model)
486 {
487 struct mx6_ddr3_cfg *mem = NULL;
488 struct mx6_mmdc_calibration *calib = NULL;
489 struct mx6_ddr_sysinfo sysinfo = {
490 /* width of data bus:0=16,1=32,2=64 */
491 .dsize = width/32,
492 /* config for full 4GB range so that get_mem_size() works */
493 .cs_density = 32, /* 32Gb per CS */
494 /* single chip select */
495 .ncs = 1,
496 .cs1_mirror = 0,
497 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
498 #ifdef RTT_NOM_120OHM
499 .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */
500 #else
501 .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
502 #endif
503 .walat = 1, /* Write additional latency */
504 .ralat = 5, /* Read additional latency */
505 .mif3_mode = 3, /* Command prediction working mode */
506 .bi_on = 1, /* Bank interleaving enabled */
507 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
508 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
509 .pd_fast_exit = 1, /* enable precharge power-down fast exit */
510 .ddr_type = DDR_TYPE_DDR3,
511 .refsel = 1, /* Refresh cycles at 32KHz */
512 .refr = 7, /* 8 refresh commands per refresh cycle */
513 };
514
515 /*
516 * MMDC Calibration requires the following data:
517 * mx6_mmdc_calibration - board-specific calibration (routing delays)
518 * these calibration values depend on board routing, SoC, and DDR
519 * mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc)
520 * mx6_ddr_cfg - chip specific timing/layout details
521 */
522 if (width == 16 && size_mb == 128) {
523 mem = &mt41k64m16jt_125;
524 if (is_cpu_type(MXC_CPU_MX6Q))
525 ;
526 else
527 calib = &mx6sdl_64x16_mmdc_calib;
528 debug("1gB density\n");
529 } else if (width == 16 && size_mb == 256) {
530 /* 1x 2Gb density chip - same calib as 2x 2Gb */
531 mem = &mt41k128m16jt_125;
532 if (is_cpu_type(MXC_CPU_MX6Q))
533 calib = &mx6dq_128x32_mmdc_calib;
534 else
535 calib = &mx6sdl_128x32_mmdc_calib;
536 debug("2gB density\n");
537 } else if (width == 16 && size_mb == 512) {
538 mem = &mt41k256m16ha_125;
539 if (is_cpu_type(MXC_CPU_MX6Q))
540 calib = &mx6dq_256x16_mmdc_calib;
541 else
542 calib = &mx6sdl_256x16_mmdc_calib;
543 debug("4gB density\n");
544 } else if (width == 16 && size_mb == 1024) {
545 mem = &mt41k512m16ha_125;
546 if (is_cpu_type(MXC_CPU_MX6Q))
547 calib = &mx6dq_512x32_mmdc_calib;
548 debug("8gB density\n");
549 } else if (width == 32 && size_mb == 256) {
550 /* Same calib as width==16, size==128 */
551 mem = &mt41k64m16jt_125;
552 if (is_cpu_type(MXC_CPU_MX6Q))
553 ;
554 else
555 calib = &mx6sdl_64x16_mmdc_calib;
556 debug("1gB density\n");
557 } else if (width == 32 && size_mb == 512) {
558 mem = &mt41k128m16jt_125;
559 if (is_cpu_type(MXC_CPU_MX6Q))
560 calib = &mx6dq_128x32_mmdc_calib;
561 else
562 calib = &mx6sdl_128x32_mmdc_calib;
563 debug("2gB density\n");
564 } else if (width == 32 && size_mb == 1024) {
565 mem = &mt41k256m16ha_125;
566 if (is_cpu_type(MXC_CPU_MX6Q))
567 calib = &mx6dq_256x32_mmdc_calib;
568 else
569 calib = &mx6sdl_256x32_mmdc_calib;
570 debug("4gB density\n");
571 } else if (width == 32 && size_mb == 2048) {
572 mem = &mt41k512m16ha_125;
573 if (is_cpu_type(MXC_CPU_MX6Q))
574 calib = &mx6dq_512x32_mmdc_calib;
575 debug("8gB density\n");
576 } else if (width == 64 && size_mb == 512) {
577 mem = &mt41k64m16jt_125;
578 debug("1gB density\n");
579 if (is_cpu_type(MXC_CPU_MX6Q))
580 calib = &mx6dq_64x64_mmdc_calib;
581 else
582 calib = &mx6sdl_64x64_mmdc_calib;
583 } else if (width == 64 && size_mb == 1024) {
584 mem = &mt41k128m16jt_125;
585 if (is_cpu_type(MXC_CPU_MX6Q))
586 calib = &mx6dq_128x64_mmdc_calib;
587 else
588 calib = &mx6sdl_128x64_mmdc_calib;
589 debug("2gB density\n");
590 } else if (width == 64 && size_mb == 2048) {
591 switch(board_model) {
592 case GW5905:
593 /* 8xMT41K128M16 (2GiB) fly-by mirrored 2-chipsels */
594 mem = &mt41k128m16jt_125;
595 debug("2gB density - 2 chipsel\n");
596 if (!is_cpu_type(MXC_CPU_MX6Q)) {
597 calib = &mx6sdl_128x64x2_mmdc_calib;
598 sysinfo.ncs = 2;
599 sysinfo.cs_density = 10; /* CS0_END=39 */
600 sysinfo.cs1_mirror = 1; /* mirror enabled */
601 }
602 break;
603 default:
604 mem = &mt41k256m16ha_125;
605 if (is_cpu_type(MXC_CPU_MX6Q))
606 calib = &mx6dq_256x64_mmdc_calib;
607 else
608 calib = &mx6sdl_256x64_mmdc_calib;
609 debug("4gB density\n");
610 break;
611 }
612 } else if (width == 64 && size_mb == 4096) {
613 switch(board_model) {
614 case GW5903:
615 /* 8xMT41K256M16 (4GiB) fly-by mirrored 2-chipsels */
616 mem = &mt41k256m16ha_125;
617 debug("4gB density - 2 chipsel\n");
618 if (!is_cpu_type(MXC_CPU_MX6Q)) {
619 calib = &mx6sdl_256x64x2_mmdc_calib;
620 sysinfo.ncs = 2;
621 sysinfo.cs_density = 18; /* CS0_END=71 */
622 sysinfo.cs1_mirror = 1; /* mirror enabled */
623 }
624 break;
625 default:
626 mem = &mt41k512m16ha_125;
627 if (is_cpu_type(MXC_CPU_MX6Q))
628 calib = &mx6dq_512x64_mmdc_calib;
629 debug("8gB density\n");
630 break;
631 }
632 }
633
634 if (!(mem && calib)) {
635 puts("Error: Invalid Calibration/Board Configuration\n");
636 printf("MEM : %s\n", mem ? "OKAY" : "NULL");
637 printf("CALIB : %s\n", calib ? "OKAY" : "NULL");
638 printf("CPUTYPE: %s\n",
639 is_cpu_type(MXC_CPU_MX6Q) ? "IMX6Q" : "IMX6DL");
640 printf("SIZE_MB: %d\n", size_mb);
641 printf("WIDTH : %d\n", width);
642 hang();
643 }
644
645 if (is_cpu_type(MXC_CPU_MX6Q))
646 mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs,
647 &mx6dq_grp_ioregs);
648 else
649 mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs,
650 &mx6sdl_grp_ioregs);
651 mx6_dram_cfg(&sysinfo, calib, mem);
652 }
653
ccgr_init(void)654 static void ccgr_init(void)
655 {
656 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
657
658 writel(0x00C03F3F, &ccm->CCGR0);
659 writel(0x0030FC03, &ccm->CCGR1);
660 writel(0x0FFFC000, &ccm->CCGR2);
661 writel(0x3FF00000, &ccm->CCGR3);
662 writel(0xFFFFF300, &ccm->CCGR4); /* enable NAND/GPMI/BCH clks */
663 writel(0x0F0000C3, &ccm->CCGR5);
664 writel(0x000003FF, &ccm->CCGR6);
665 }
666
667 /*
668 * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
669 * - we have a stack and a place to store GD, both in SRAM
670 * - no variable global data is available
671 */
board_init_f(ulong dummy)672 void board_init_f(ulong dummy)
673 {
674 struct ventana_board_info ventana_info;
675 int board_model;
676
677 /* setup clock gating */
678 ccgr_init();
679
680 /* setup AIPS and disable watchdog */
681 arch_cpu_init();
682
683 /* setup AXI */
684 gpr_init();
685
686 /* iomux and setup of uart/i2c */
687 setup_iomux_uart();
688 setup_ventana_i2c(0);
689 setup_ventana_i2c(1);
690
691 /* setup GP timer */
692 timer_init();
693
694 /* UART clocks enabled and gd valid - init serial console */
695 preloader_console_init();
696
697 /* read/validate EEPROM info to determine board model and SDRAM cfg */
698 board_model = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
699
700 /* configure model-specific gpio */
701 setup_iomux_gpio(board_model, &ventana_info);
702
703 /* provide some some default: 32bit 128MB */
704 if (GW_UNKNOWN == board_model)
705 hang();
706
707 /* configure MMDC for SDRAM width/size and per-model calibration */
708 spl_dram_init(8 << ventana_info.sdram_width,
709 16 << ventana_info.sdram_size,
710 board_model);
711 }
712
board_boot_order(u32 * spl_boot_list)713 void board_boot_order(u32 *spl_boot_list)
714 {
715 spl_boot_list[0] = spl_boot_device();
716 switch (spl_boot_list[0]) {
717 case BOOT_DEVICE_NAND:
718 spl_boot_list[1] = BOOT_DEVICE_MMC1;
719 spl_boot_list[2] = BOOT_DEVICE_UART;
720 break;
721 case BOOT_DEVICE_MMC1:
722 spl_boot_list[1] = BOOT_DEVICE_UART;
723 break;
724 }
725 }
726
727 /* called from board_init_r after gd setup if CONFIG_SPL_BOARD_INIT defined */
728 /* its our chance to print info about boot device */
spl_board_init(void)729 void spl_board_init(void)
730 {
731 /* determine boot device from SRC_SBMR1 (BOOT_CFG[4:1]) or SRC_GPR9 */
732 u32 boot_device = spl_boot_device();
733
734 switch (boot_device) {
735 case BOOT_DEVICE_MMC1:
736 puts("Booting from MMC\n");
737 break;
738 case BOOT_DEVICE_NAND:
739 puts("Booting from NAND\n");
740 break;
741 case BOOT_DEVICE_SATA:
742 puts("Booting from SATA\n");
743 break;
744 default:
745 puts("Unknown boot device\n");
746 }
747
748 /* PMIC init */
749 setup_pmic();
750 }
751
752 #ifdef CONFIG_SPL_OS_BOOT
753 /* return 1 if we wish to boot to uboot vs os (falcon mode) */
spl_start_uboot(void)754 int spl_start_uboot(void)
755 {
756 unsigned char ret = 1;
757
758 debug("%s\n", __func__);
759 #ifdef CONFIG_SPL_ENV_SUPPORT
760 env_init();
761 env_load();
762 debug("boot_os=%s\n", env_get("boot_os"));
763 if (env_get_yesno("boot_os") == 1)
764 ret = 0;
765 #else
766 /* use i2c-0:0x50:0x00 for falcon boot mode (0=linux, else uboot) */
767 i2c_set_bus_num(0);
768 gsc_i2c_read(0x50, 0x0, 1, &ret, 1);
769 #endif
770 if (!ret)
771 gsc_boot_wd_disable();
772
773 debug("%s booting %s\n", __func__, ret ? "uboot" : "linux");
774 return ret;
775 }
776 #endif
777