1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2010
4 * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
5 */
6
7 #ifdef CONFIG_GDSYS_LEGACY_DRIVERS
8
9 #include <common.h>
10 #include <i2c.h>
11 #include <malloc.h>
12
13 #include "ch7301.h"
14 #include "dp501.h"
15 #include <gdsys_fpga.h>
16
17 #define ICS8N3QV01_I2C_ADDR 0x6E
18 #define ICS8N3QV01_FREF 114285000
19 #define ICS8N3QV01_FREF_LL 114285000LL
20 #define ICS8N3QV01_F_DEFAULT_0 156250000LL
21 #define ICS8N3QV01_F_DEFAULT_1 125000000LL
22 #define ICS8N3QV01_F_DEFAULT_2 100000000LL
23 #define ICS8N3QV01_F_DEFAULT_3 25175000LL
24
25 #define SIL1178_MASTER_I2C_ADDRESS 0x38
26 #define SIL1178_SLAVE_I2C_ADDRESS 0x39
27
28 #define PIXCLK_640_480_60 25180000
29 #define MAX_X_CHARS 53
30 #define MAX_Y_CHARS 26
31
32 #ifdef CONFIG_SYS_OSD_DH
33 #define MAX_OSD_SCREEN 8
34 #define OSD_DH_BASE 4
35 #else
36 #define MAX_OSD_SCREEN 4
37 #endif
38
39 #ifdef CONFIG_SYS_OSD_DH
40 #define OSD_SET_REG(screen, fld, val) \
41 do { \
42 if (screen >= OSD_DH_BASE) \
43 FPGA_SET_REG(screen - OSD_DH_BASE, osd1.fld, val); \
44 else \
45 FPGA_SET_REG(screen, osd0.fld, val); \
46 } while (0)
47 #else
48 #define OSD_SET_REG(screen, fld, val) \
49 FPGA_SET_REG(screen, osd0.fld, val)
50 #endif
51
52 #ifdef CONFIG_SYS_OSD_DH
53 #define OSD_GET_REG(screen, fld, val) \
54 do { \
55 if (screen >= OSD_DH_BASE) \
56 FPGA_GET_REG(screen - OSD_DH_BASE, osd1.fld, val); \
57 else \
58 FPGA_GET_REG(screen, osd0.fld, val); \
59 } while (0)
60 #else
61 #define OSD_GET_REG(screen, fld, val) \
62 FPGA_GET_REG(screen, osd0.fld, val)
63 #endif
64
65 unsigned int base_width;
66 unsigned int base_height;
67 size_t bufsize;
68 u16 *buf;
69
70 unsigned int osd_screen_mask = 0;
71
72 #ifdef CONFIG_SYS_ICS8N3QV01_I2C
73 int ics8n3qv01_i2c[] = CONFIG_SYS_ICS8N3QV01_I2C;
74 #endif
75
76 #ifdef CONFIG_SYS_SIL1178_I2C
77 int sil1178_i2c[] = CONFIG_SYS_SIL1178_I2C;
78 #endif
79
80 #ifdef CONFIG_SYS_MPC92469AC
mpc92469ac_calc_parameters(unsigned int fout,unsigned int * post_div,unsigned int * feedback_div)81 static void mpc92469ac_calc_parameters(unsigned int fout,
82 unsigned int *post_div, unsigned int *feedback_div)
83 {
84 unsigned int n = *post_div;
85 unsigned int m = *feedback_div;
86 unsigned int a;
87 unsigned int b = 14745600 / 16;
88
89 if (fout < 50169600)
90 n = 8;
91 else if (fout < 100339199)
92 n = 4;
93 else if (fout < 200678399)
94 n = 2;
95 else
96 n = 1;
97
98 a = fout * n + (b / 2); /* add b/2 for proper rounding */
99
100 m = a / b;
101
102 *post_div = n;
103 *feedback_div = m;
104 }
105
mpc92469ac_set(unsigned screen,unsigned int fout)106 static void mpc92469ac_set(unsigned screen, unsigned int fout)
107 {
108 unsigned int n;
109 unsigned int m;
110 unsigned int bitval = 0;
111 mpc92469ac_calc_parameters(fout, &n, &m);
112
113 switch (n) {
114 case 1:
115 bitval = 0x00;
116 break;
117 case 2:
118 bitval = 0x01;
119 break;
120 case 4:
121 bitval = 0x02;
122 break;
123 case 8:
124 bitval = 0x03;
125 break;
126 }
127
128 FPGA_SET_REG(screen, mpc3w_control, (bitval << 9) | m);
129 }
130 #endif
131
132 #ifdef CONFIG_SYS_ICS8N3QV01_I2C
133
ics8n3qv01_get_fout_calc(unsigned index)134 static unsigned int ics8n3qv01_get_fout_calc(unsigned index)
135 {
136 unsigned long long n;
137 unsigned long long mint;
138 unsigned long long mfrac;
139 u8 reg_a, reg_b, reg_c, reg_d, reg_f;
140 unsigned long long fout_calc;
141
142 if (index > 3)
143 return 0;
144
145 reg_a = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 0 + index);
146 reg_b = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 4 + index);
147 reg_c = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 8 + index);
148 reg_d = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 12 + index);
149 reg_f = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 20 + index);
150
151 mint = ((reg_a >> 1) & 0x1f) | (reg_f & 0x20);
152 mfrac = ((reg_a & 0x01) << 17) | (reg_b << 9) | (reg_c << 1)
153 | (reg_d >> 7);
154 n = reg_d & 0x7f;
155
156 fout_calc = (mint * ICS8N3QV01_FREF_LL
157 + mfrac * ICS8N3QV01_FREF_LL / 262144LL
158 + ICS8N3QV01_FREF_LL / 524288LL
159 + n / 2)
160 / n
161 * 1000000
162 / (1000000 - 100);
163
164 return fout_calc;
165 }
166
167
ics8n3qv01_calc_parameters(unsigned int fout,unsigned int * _mint,unsigned int * _mfrac,unsigned int * _n)168 static void ics8n3qv01_calc_parameters(unsigned int fout,
169 unsigned int *_mint, unsigned int *_mfrac,
170 unsigned int *_n)
171 {
172 unsigned int n;
173 unsigned int foutiic;
174 unsigned int fvcoiic;
175 unsigned int mint;
176 unsigned long long mfrac;
177
178 n = (2215000000U + fout / 2) / fout;
179 if ((n & 1) && (n > 5))
180 n -= 1;
181
182 foutiic = fout - (fout / 10000);
183 fvcoiic = foutiic * n;
184
185 mint = fvcoiic / 114285000;
186 if ((mint < 17) || (mint > 63))
187 printf("ics8n3qv01_calc_parameters: cannot determine mint\n");
188
189 mfrac = ((unsigned long long)fvcoiic % 114285000LL) * 262144LL
190 / 114285000LL;
191
192 *_mint = mint;
193 *_mfrac = mfrac;
194 *_n = n;
195 }
196
ics8n3qv01_set(unsigned int fout)197 static void ics8n3qv01_set(unsigned int fout)
198 {
199 unsigned int n;
200 unsigned int mint;
201 unsigned int mfrac;
202 unsigned int fout_calc;
203 unsigned long long fout_prog;
204 long long off_ppm;
205 u8 reg0, reg4, reg8, reg12, reg18, reg20;
206
207 fout_calc = ics8n3qv01_get_fout_calc(1);
208 off_ppm = (fout_calc - ICS8N3QV01_F_DEFAULT_1) * 1000000
209 / ICS8N3QV01_F_DEFAULT_1;
210 printf(" PLL is off by %lld ppm\n", off_ppm);
211 fout_prog = (unsigned long long)fout * (unsigned long long)fout_calc
212 / ICS8N3QV01_F_DEFAULT_1;
213 ics8n3qv01_calc_parameters(fout_prog, &mint, &mfrac, &n);
214
215 reg0 = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 0) & 0xc0;
216 reg0 |= (mint & 0x1f) << 1;
217 reg0 |= (mfrac >> 17) & 0x01;
218 i2c_reg_write(ICS8N3QV01_I2C_ADDR, 0, reg0);
219
220 reg4 = mfrac >> 9;
221 i2c_reg_write(ICS8N3QV01_I2C_ADDR, 4, reg4);
222
223 reg8 = mfrac >> 1;
224 i2c_reg_write(ICS8N3QV01_I2C_ADDR, 8, reg8);
225
226 reg12 = mfrac << 7;
227 reg12 |= n & 0x7f;
228 i2c_reg_write(ICS8N3QV01_I2C_ADDR, 12, reg12);
229
230 reg18 = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 18) & 0x03;
231 reg18 |= 0x20;
232 i2c_reg_write(ICS8N3QV01_I2C_ADDR, 18, reg18);
233
234 reg20 = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 20) & 0x1f;
235 reg20 |= mint & (1 << 5);
236 i2c_reg_write(ICS8N3QV01_I2C_ADDR, 20, reg20);
237 }
238 #endif
239
osd_write_videomem(unsigned screen,unsigned offset,u16 * data,size_t charcount)240 static int osd_write_videomem(unsigned screen, unsigned offset,
241 u16 *data, size_t charcount)
242 {
243 unsigned int k;
244
245 for (k = 0; k < charcount; ++k) {
246 if (offset + k >= bufsize)
247 return -1;
248 #ifdef CONFIG_SYS_OSD_DH
249 if (screen >= OSD_DH_BASE)
250 FPGA_SET_REG(screen - OSD_DH_BASE,
251 videomem1[offset + k], data[k]);
252 else
253 FPGA_SET_REG(screen, videomem0[offset + k], data[k]);
254 #else
255 FPGA_SET_REG(screen, videomem0[offset + k], data[k]);
256 #endif
257 }
258
259 return charcount;
260 }
261
osd_print(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])262 static int osd_print(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
263 {
264 unsigned screen;
265
266 if (argc < 5) {
267 cmd_usage(cmdtp);
268 return 1;
269 }
270
271 for (screen = 0; screen < MAX_OSD_SCREEN; ++screen) {
272 unsigned x;
273 unsigned y;
274 unsigned charcount;
275 unsigned len;
276 u8 color;
277 unsigned int k;
278 char *text;
279 int res;
280
281 if (!(osd_screen_mask & (1 << screen)))
282 continue;
283
284 x = simple_strtoul(argv[1], NULL, 16);
285 y = simple_strtoul(argv[2], NULL, 16);
286 color = simple_strtoul(argv[3], NULL, 16);
287 text = argv[4];
288 charcount = strlen(text);
289 len = (charcount > bufsize) ? bufsize : charcount;
290
291 for (k = 0; k < len; ++k)
292 buf[k] = (text[k] << 8) | color;
293
294 res = osd_write_videomem(screen, y * base_width + x, buf, len);
295 if (res < 0)
296 return res;
297
298 OSD_SET_REG(screen, control, 0x0049);
299 }
300
301 return 0;
302 }
303
osd_probe(unsigned screen)304 int osd_probe(unsigned screen)
305 {
306 u16 version;
307 u16 features;
308 int old_bus = i2c_get_bus_num();
309 bool pixclock_present = false;
310 bool output_driver_present = false;
311
312 OSD_GET_REG(0, version, &version);
313 OSD_GET_REG(0, features, &features);
314
315 base_width = ((features & 0x3f00) >> 8) + 1;
316 base_height = (features & 0x001f) + 1;
317 bufsize = base_width * base_height;
318 buf = malloc(sizeof(u16) * bufsize);
319 if (!buf)
320 return -1;
321
322 #ifdef CONFIG_SYS_OSD_DH
323 printf("OSD%d-%d: Digital-OSD version %01d.%02d, %d" "x%d characters\n",
324 (screen >= OSD_DH_BASE) ? (screen - OSD_DH_BASE) : screen,
325 (screen > 3) ? 1 : 0, version/100, version%100, base_width,
326 base_height);
327 #else
328 printf("OSD%d: Digital-OSD version %01d.%02d, %d" "x%d characters\n",
329 screen, version/100, version%100, base_width, base_height);
330 #endif
331 /* setup pixclock */
332
333 #ifdef CONFIG_SYS_MPC92469AC
334 pixclock_present = true;
335 mpc92469ac_set(screen, PIXCLK_640_480_60);
336 #endif
337
338 #ifdef CONFIG_SYS_ICS8N3QV01_I2C
339 i2c_set_bus_num(ics8n3qv01_i2c[screen]);
340 if (!i2c_probe(ICS8N3QV01_I2C_ADDR)) {
341 ics8n3qv01_set(PIXCLK_640_480_60);
342 pixclock_present = true;
343 }
344 #endif
345
346 if (!pixclock_present)
347 printf(" no pixelclock found\n");
348
349 /* setup output driver */
350
351 #ifdef CONFIG_SYS_CH7301_I2C
352 if (!ch7301_probe(screen, true))
353 output_driver_present = true;
354 #endif
355
356 #ifdef CONFIG_SYS_SIL1178_I2C
357 i2c_set_bus_num(sil1178_i2c[screen]);
358 if (!i2c_probe(SIL1178_SLAVE_I2C_ADDRESS)) {
359 if (i2c_reg_read(SIL1178_SLAVE_I2C_ADDRESS, 0x02) == 0x06) {
360 /*
361 * magic initialization sequence,
362 * adapted from datasheet
363 */
364 i2c_reg_write(SIL1178_SLAVE_I2C_ADDRESS, 0x08, 0x36);
365 i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x44);
366 i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x4c);
367 i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0e, 0x10);
368 i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0a, 0x80);
369 i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x09, 0x30);
370 i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0c, 0x89);
371 i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0d, 0x60);
372 i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x36);
373 i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x37);
374 output_driver_present = true;
375 }
376 }
377 #endif
378
379 #ifdef CONFIG_SYS_DP501_I2C
380 if (!dp501_probe(screen, true))
381 output_driver_present = true;
382 #endif
383
384 if (!output_driver_present)
385 printf(" no output driver found\n");
386
387 OSD_SET_REG(screen, xy_size, ((32 - 1) << 8) | (16 - 1));
388 OSD_SET_REG(screen, x_pos, 0x007f);
389 OSD_SET_REG(screen, y_pos, 0x005f);
390
391 if (pixclock_present && output_driver_present)
392 osd_screen_mask |= 1 << screen;
393
394 i2c_set_bus_num(old_bus);
395
396 return 0;
397 }
398
osd_write(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])399 int osd_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
400 {
401 unsigned screen;
402
403 if ((argc < 4) || (strlen(argv[3]) % 4)) {
404 cmd_usage(cmdtp);
405 return 1;
406 }
407
408 for (screen = 0; screen < MAX_OSD_SCREEN; ++screen) {
409 unsigned x;
410 unsigned y;
411 unsigned k;
412 u16 buffer[base_width];
413 char *rp;
414 u16 *wp = buffer;
415 unsigned count = (argc > 4) ?
416 simple_strtoul(argv[4], NULL, 16) : 1;
417
418 if (!(osd_screen_mask & (1 << screen)))
419 continue;
420
421 x = simple_strtoul(argv[1], NULL, 16);
422 y = simple_strtoul(argv[2], NULL, 16);
423 rp = argv[3];
424
425
426 while (*rp) {
427 char substr[5];
428
429 memcpy(substr, rp, 4);
430 substr[4] = 0;
431 *wp = simple_strtoul(substr, NULL, 16);
432
433 rp += 4;
434 wp++;
435 if (wp - buffer > base_width)
436 break;
437 }
438
439 for (k = 0; k < count; ++k) {
440 unsigned offset =
441 y * base_width + x + k * (wp - buffer);
442 osd_write_videomem(screen, offset, buffer,
443 wp - buffer);
444 }
445
446 OSD_SET_REG(screen, control, 0x0049);
447 }
448
449 return 0;
450 }
451
osd_size(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])452 int osd_size(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
453 {
454 unsigned screen;
455 unsigned x;
456 unsigned y;
457
458 if (argc < 3) {
459 cmd_usage(cmdtp);
460 return 1;
461 }
462
463 x = simple_strtoul(argv[1], NULL, 16);
464 y = simple_strtoul(argv[2], NULL, 16);
465
466 if (!x || (x > 64) || (x > MAX_X_CHARS) ||
467 !y || (y > 32) || (y > MAX_Y_CHARS)) {
468 cmd_usage(cmdtp);
469 return 1;
470 }
471
472 for (screen = 0; screen < MAX_OSD_SCREEN; ++screen) {
473 if (!(osd_screen_mask & (1 << screen)))
474 continue;
475
476 OSD_SET_REG(screen, xy_size, ((x - 1) << 8) | (y - 1));
477 OSD_SET_REG(screen, x_pos, 32767 * (640 - 12 * x) / 65535);
478 OSD_SET_REG(screen, y_pos, 32767 * (480 - 18 * y) / 65535);
479 }
480
481 return 0;
482 }
483
484 U_BOOT_CMD(
485 osdw, 5, 0, osd_write,
486 "write 16-bit hex encoded buffer to osd memory",
487 "pos_x pos_y buffer count\n"
488 );
489
490 U_BOOT_CMD(
491 osdp, 5, 0, osd_print,
492 "write ASCII buffer to osd memory",
493 "pos_x pos_y color text\n"
494 );
495
496 U_BOOT_CMD(
497 osdsize, 3, 0, osd_size,
498 "set OSD XY size in characters",
499 "size_x(max. " __stringify(MAX_X_CHARS)
500 ") size_y(max. " __stringify(MAX_Y_CHARS) ")\n"
501 );
502
503 #endif /* CONFIG_GDSYS_LEGACY_DRIVERS */