1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2014
4 * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
5 */
6
7 #include <common.h>
8 #include <env.h>
9 #include <hwconfig.h>
10 #include <i2c.h>
11 #include <init.h>
12 #include <spi.h>
13 #include <linux/libfdt.h>
14 #include <fdt_support.h>
15 #include <pci.h>
16 #include <mpc83xx.h>
17 #include <fsl_esdhc.h>
18 #include <asm/io.h>
19 #include <asm/fsl_serdes.h>
20 #include <asm/fsl_mpc83xx_serdes.h>
21
22 #include "mpc8308.h"
23
24 #include <gdsys_fpga.h>
25
26 #include "../common/adv7611.h"
27 #include "../common/ch7301.h"
28 #include "../common/dp501.h"
29 #include "../common/ioep-fpga.h"
30 #include "../common/mclink.h"
31 #include "../common/osd.h"
32 #include "../common/phy.h"
33 #include "../common/fanctrl.h"
34
35 #include <pca953x.h>
36 #include <pca9698.h>
37
38 #include <miiphy.h>
39
40 #define MAX_MUX_CHANNELS 2
41
42 enum {
43 MCFPGA_DONE = 1 << 0,
44 MCFPGA_INIT_N = 1 << 1,
45 MCFPGA_PROGRAM_N = 1 << 2,
46 MCFPGA_UPDATE_ENABLE_N = 1 << 3,
47 MCFPGA_RESET_N = 1 << 4,
48 };
49
50 enum {
51 GPIO_MDC = 1 << 14,
52 GPIO_MDIO = 1 << 15,
53 };
54
55 uint mclink_fpgacount;
56 struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
57
58 struct {
59 u8 bus;
60 u8 addr;
61 } strider_fans[] = CONFIG_STRIDER_FANS;
62
fpga_set_reg(u32 fpga,u16 * reg,off_t regoff,u16 data)63 int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
64 {
65 int res;
66
67 switch (fpga) {
68 case 0:
69 out_le16(reg, data);
70 break;
71 default:
72 res = mclink_send(fpga - 1, regoff, data);
73 if (res < 0) {
74 printf("mclink_send reg %02lx data %04x returned %d\n",
75 regoff, data, res);
76 return res;
77 }
78 break;
79 }
80
81 return 0;
82 }
83
fpga_get_reg(u32 fpga,u16 * reg,off_t regoff,u16 * data)84 int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
85 {
86 int res;
87
88 switch (fpga) {
89 case 0:
90 *data = in_le16(reg);
91 break;
92 default:
93 if (fpga > mclink_fpgacount)
94 return -EINVAL;
95 res = mclink_receive(fpga - 1, regoff, data);
96 if (res < 0) {
97 printf("mclink_receive reg %02lx returned %d\n",
98 regoff, res);
99 return res;
100 }
101 }
102
103 return 0;
104 }
105
checkboard(void)106 int checkboard(void)
107 {
108 char *s = env_get("serial#");
109 bool hw_type_cat = pca9698_get_value(0x20, 18);
110
111 puts("Board: ");
112
113 printf("Strider %s", hw_type_cat ? "CAT" : "Fiber");
114
115 if (s) {
116 puts(", serial# ");
117 puts(s);
118 }
119
120 puts("\n");
121
122 return 0;
123 }
124
last_stage_init(void)125 int last_stage_init(void)
126 {
127 int slaves;
128 uint k;
129 uint mux_ch;
130 uchar mclink_controllers_dvi[] = { 0x3c, 0x3d, 0x3e };
131 #ifdef CONFIG_STRIDER_CPU
132 uchar mclink_controllers_dp[] = { 0x24, 0x25, 0x26 };
133 #endif
134 bool hw_type_cat = pca9698_get_value(0x20, 18);
135 #ifdef CONFIG_STRIDER_CON_DP
136 bool is_dh = pca9698_get_value(0x20, 25);
137 #endif
138 bool ch0_sgmii2_present;
139
140 /* Turn on Analog Devices ADV7611 */
141 pca9698_direction_output(0x20, 8, 0);
142
143 /* Turn on Parade DP501 */
144 pca9698_direction_output(0x20, 10, 1);
145 pca9698_direction_output(0x20, 11, 1);
146
147 ch0_sgmii2_present = !pca9698_get_value(0x20, 37);
148
149 /* wait for FPGA done, then reset FPGA */
150 for (k = 0; k < ARRAY_SIZE(mclink_controllers_dvi); ++k) {
151 uint ctr = 0;
152 uchar *mclink_controllers = mclink_controllers_dvi;
153
154 #ifdef CONFIG_STRIDER_CPU
155 if (i2c_probe(mclink_controllers[k])) {
156 mclink_controllers = mclink_controllers_dp;
157 if (i2c_probe(mclink_controllers[k]))
158 continue;
159 }
160 #else
161 if (i2c_probe(mclink_controllers[k]))
162 continue;
163 #endif
164 while (!(pca953x_get_val(mclink_controllers[k])
165 & MCFPGA_DONE)) {
166 mdelay(100);
167 if (ctr++ > 5) {
168 printf("no done for mclink_controller %d\n", k);
169 break;
170 }
171 }
172
173 pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0);
174 pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0);
175 udelay(10);
176 pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N,
177 MCFPGA_RESET_N);
178 }
179
180 if (hw_type_cat) {
181 int retval;
182 struct mii_dev *mdiodev = mdio_alloc();
183
184 if (!mdiodev)
185 return -ENOMEM;
186 strncpy(mdiodev->name, bb_miiphy_buses[0].name, MDIO_NAME_LEN);
187 mdiodev->read = bb_miiphy_read;
188 mdiodev->write = bb_miiphy_write;
189
190 retval = mdio_register(mdiodev);
191 if (retval < 0)
192 return retval;
193 for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) {
194 if ((mux_ch == 1) && !ch0_sgmii2_present)
195 continue;
196
197 setup_88e1514(bb_miiphy_buses[0].name, mux_ch);
198 }
199 }
200
201 /* give slave-PLLs and Parade DP501 some time to be up and running */
202 mdelay(500);
203
204 mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
205 slaves = mclink_probe();
206 mclink_fpgacount = 0;
207
208 ioep_fpga_print_info(0);
209
210 if (!adv7611_probe(0))
211 printf(" Advantiv ADV7611 HDMI Receiver\n");
212
213 #ifdef CONFIG_STRIDER_CON
214 if (ioep_fpga_has_osd(0))
215 osd_probe(0);
216 #endif
217
218 #ifdef CONFIG_STRIDER_CON_DP
219 if (ioep_fpga_has_osd(0)) {
220 osd_probe(0);
221 if (is_dh)
222 osd_probe(4);
223 }
224 #endif
225
226 #ifdef CONFIG_STRIDER_CPU
227 ch7301_probe(0, false);
228 dp501_probe(0, false);
229 #endif
230
231 if (slaves <= 0)
232 return 0;
233
234 mclink_fpgacount = slaves;
235
236 #ifdef CONFIG_STRIDER_CPU
237 /* get ADV7611 out of reset, power up DP501, give some time to wakeup */
238 for (k = 1; k <= slaves; ++k)
239 FPGA_SET_REG(k, extended_control, 0x10); /* enable video */
240
241 mdelay(500);
242 #endif
243
244 for (k = 1; k <= slaves; ++k) {
245 ioep_fpga_print_info(k);
246 #ifdef CONFIG_STRIDER_CON
247 if (ioep_fpga_has_osd(k))
248 osd_probe(k);
249 #endif
250 #ifdef CONFIG_STRIDER_CON_DP
251 if (ioep_fpga_has_osd(k)) {
252 osd_probe(k);
253 if (is_dh)
254 osd_probe(k + 4);
255 }
256 #endif
257 #ifdef CONFIG_STRIDER_CPU
258 if (!adv7611_probe(k))
259 printf(" Advantiv ADV7611 HDMI Receiver\n");
260 ch7301_probe(k, false);
261 dp501_probe(k, false);
262 #endif
263 if (hw_type_cat) {
264 int retval;
265 struct mii_dev *mdiodev = mdio_alloc();
266
267 if (!mdiodev)
268 return -ENOMEM;
269 strncpy(mdiodev->name, bb_miiphy_buses[k].name,
270 MDIO_NAME_LEN);
271 mdiodev->read = bb_miiphy_read;
272 mdiodev->write = bb_miiphy_write;
273
274 retval = mdio_register(mdiodev);
275 if (retval < 0)
276 return retval;
277 setup_88e1514(bb_miiphy_buses[k].name, 0);
278 }
279 }
280
281 for (k = 0; k < ARRAY_SIZE(strider_fans); ++k) {
282 i2c_set_bus_num(strider_fans[k].bus);
283 init_fan_controller(strider_fans[k].addr);
284 }
285
286 return 0;
287 }
288
289 /*
290 * provide access to fpga gpios (for I2C bitbang)
291 * (these may look all too simple but make iocon.h much more readable)
292 */
fpga_gpio_set(uint bus,int pin)293 void fpga_gpio_set(uint bus, int pin)
294 {
295 FPGA_SET_REG(bus, gpio.set, pin);
296 }
297
fpga_gpio_clear(uint bus,int pin)298 void fpga_gpio_clear(uint bus, int pin)
299 {
300 FPGA_SET_REG(bus, gpio.clear, pin);
301 }
302
fpga_gpio_get(uint bus,int pin)303 int fpga_gpio_get(uint bus, int pin)
304 {
305 u16 val;
306
307 FPGA_GET_REG(bus, gpio.read, &val);
308
309 return val & pin;
310 }
311
312 #ifdef CONFIG_STRIDER_CON_DP
fpga_control_set(uint bus,int pin)313 void fpga_control_set(uint bus, int pin)
314 {
315 u16 val;
316
317 FPGA_GET_REG(bus, control, &val);
318 FPGA_SET_REG(bus, control, val | pin);
319 }
320
fpga_control_clear(uint bus,int pin)321 void fpga_control_clear(uint bus, int pin)
322 {
323 u16 val;
324
325 FPGA_GET_REG(bus, control, &val);
326 FPGA_SET_REG(bus, control, val & ~pin);
327 }
328 #endif
329
mpc8308_init(void)330 void mpc8308_init(void)
331 {
332 pca9698_direction_output(0x20, 26, 1);
333 }
334
mpc8308_set_fpga_reset(uint state)335 void mpc8308_set_fpga_reset(uint state)
336 {
337 pca9698_set_value(0x20, 26, state ? 0 : 1);
338 }
339
mpc8308_setup_hw(void)340 void mpc8308_setup_hw(void)
341 {
342 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
343
344 /*
345 * set "startup-finished"-gpios
346 */
347 setbits_be32(&immr->gpio[0].dir, BIT(31 - 11) | BIT(31 - 12));
348 setbits_gpio0_out(BIT(31 - 12));
349 }
350
mpc8308_get_fpga_done(uint fpga)351 int mpc8308_get_fpga_done(uint fpga)
352 {
353 return pca9698_get_value(0x20, 20);
354 }
355
356 #ifdef CONFIG_FSL_ESDHC
board_mmc_init(bd_t * bd)357 int board_mmc_init(bd_t *bd)
358 {
359 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
360 sysconf83xx_t *sysconf = &immr->sysconf;
361
362 /* Enable cache snooping in eSDHC system configuration register */
363 out_be32(&sysconf->sdhccr, 0x02000000);
364
365 return fsl_esdhc_mmc_init(bd);
366 }
367 #endif
368
369 static struct pci_region pcie_regions_0[] = {
370 {
371 .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
372 .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
373 .size = CONFIG_SYS_PCIE1_MEM_SIZE,
374 .flags = PCI_REGION_MEM,
375 },
376 {
377 .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
378 .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
379 .size = CONFIG_SYS_PCIE1_IO_SIZE,
380 .flags = PCI_REGION_IO,
381 },
382 };
383
pci_init_board(void)384 void pci_init_board(void)
385 {
386 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
387 sysconf83xx_t *sysconf = &immr->sysconf;
388 law83xx_t *pcie_law = sysconf->pcielaw;
389 struct pci_region *pcie_reg[] = { pcie_regions_0 };
390
391 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
392 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
393
394 /* Deassert the resets in the control register */
395 out_be32(&sysconf->pecr1, 0xE0008000);
396 udelay(2000);
397
398 /* Configure PCI Express Local Access Windows */
399 out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
400 out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
401
402 mpc83xx_pcie_init(1, pcie_reg);
403 }
404
board_flash_get_legacy(ulong base,int banknum,flash_info_t * info)405 ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
406 {
407 info->portwidth = FLASH_CFI_16BIT;
408 info->chipwidth = FLASH_CFI_BY16;
409 info->interface = FLASH_CFI_X16;
410 return 1;
411 }
412
413 #if defined(CONFIG_OF_BOARD_SETUP)
ft_board_setup(void * blob,bd_t * bd)414 int ft_board_setup(void *blob, bd_t *bd)
415 {
416 ft_cpu_setup(blob, bd);
417 fsl_fdt_fixup_dr_usb(blob, bd);
418 fdt_fixup_esdhc(blob, bd);
419
420 return 0;
421 }
422 #endif
423
424 /*
425 * FPGA MII bitbang implementation
426 */
427
428 struct fpga_mii {
429 uint fpga;
430 int mdio;
431 } fpga_mii[] = {
432 { 0, 1},
433 { 1, 1},
434 { 2, 1},
435 { 3, 1},
436 };
437
mii_dummy_init(struct bb_miiphy_bus * bus)438 static int mii_dummy_init(struct bb_miiphy_bus *bus)
439 {
440 return 0;
441 }
442
mii_mdio_active(struct bb_miiphy_bus * bus)443 static int mii_mdio_active(struct bb_miiphy_bus *bus)
444 {
445 struct fpga_mii *fpga_mii = bus->priv;
446
447 if (fpga_mii->mdio)
448 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
449 else
450 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
451
452 return 0;
453 }
454
mii_mdio_tristate(struct bb_miiphy_bus * bus)455 static int mii_mdio_tristate(struct bb_miiphy_bus *bus)
456 {
457 struct fpga_mii *fpga_mii = bus->priv;
458
459 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
460
461 return 0;
462 }
463
mii_set_mdio(struct bb_miiphy_bus * bus,int v)464 static int mii_set_mdio(struct bb_miiphy_bus *bus, int v)
465 {
466 struct fpga_mii *fpga_mii = bus->priv;
467
468 if (v)
469 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
470 else
471 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
472
473 fpga_mii->mdio = v;
474
475 return 0;
476 }
477
mii_get_mdio(struct bb_miiphy_bus * bus,int * v)478 static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v)
479 {
480 u16 gpio;
481 struct fpga_mii *fpga_mii = bus->priv;
482
483 FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio);
484
485 *v = ((gpio & GPIO_MDIO) != 0);
486
487 return 0;
488 }
489
mii_set_mdc(struct bb_miiphy_bus * bus,int v)490 static int mii_set_mdc(struct bb_miiphy_bus *bus, int v)
491 {
492 struct fpga_mii *fpga_mii = bus->priv;
493
494 if (v)
495 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC);
496 else
497 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC);
498
499 return 0;
500 }
501
mii_delay(struct bb_miiphy_bus * bus)502 static int mii_delay(struct bb_miiphy_bus *bus)
503 {
504 udelay(1);
505
506 return 0;
507 }
508
509 struct bb_miiphy_bus bb_miiphy_buses[] = {
510 {
511 .name = "board0",
512 .init = mii_dummy_init,
513 .mdio_active = mii_mdio_active,
514 .mdio_tristate = mii_mdio_tristate,
515 .set_mdio = mii_set_mdio,
516 .get_mdio = mii_get_mdio,
517 .set_mdc = mii_set_mdc,
518 .delay = mii_delay,
519 .priv = &fpga_mii[0],
520 },
521 {
522 .name = "board1",
523 .init = mii_dummy_init,
524 .mdio_active = mii_mdio_active,
525 .mdio_tristate = mii_mdio_tristate,
526 .set_mdio = mii_set_mdio,
527 .get_mdio = mii_get_mdio,
528 .set_mdc = mii_set_mdc,
529 .delay = mii_delay,
530 .priv = &fpga_mii[1],
531 },
532 {
533 .name = "board2",
534 .init = mii_dummy_init,
535 .mdio_active = mii_mdio_active,
536 .mdio_tristate = mii_mdio_tristate,
537 .set_mdio = mii_set_mdio,
538 .get_mdio = mii_get_mdio,
539 .set_mdc = mii_set_mdc,
540 .delay = mii_delay,
541 .priv = &fpga_mii[2],
542 },
543 {
544 .name = "board3",
545 .init = mii_dummy_init,
546 .mdio_active = mii_mdio_active,
547 .mdio_tristate = mii_mdio_tristate,
548 .set_mdio = mii_set_mdio,
549 .get_mdio = mii_get_mdio,
550 .set_mdc = mii_set_mdc,
551 .delay = mii_delay,
552 .priv = &fpga_mii[3],
553 },
554 };
555
556 int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);
557