1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2015 Google, Inc
4 */
5
6 #include <clk.h>
7 #include <common.h>
8 #include <dm.h>
9 #include <asm/arch-rockchip/clock.h>
10 #include <dt-bindings/clock/rk3288-cru.h>
11 #include <power/regulator.h>
12
13 /*
14 * We should increase the DDR voltage to 1.2V using the PWM regulator.
15 * There is a U-Boot driver for this but it may need to add support for the
16 * 'voltage-table' property.
17 */
18 #ifndef CONFIG_SPL_BUILD
19 #if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
veyron_init(void)20 static int veyron_init(void)
21 {
22 struct udevice *dev;
23 struct clk clk;
24 int ret;
25
26 ret = regulator_get_by_platname("vdd_arm", &dev);
27 if (ret) {
28 debug("Cannot set regulator name\n");
29 return ret;
30 }
31
32 /* Slowly raise to max CPU voltage to prevent overshoot */
33 ret = regulator_set_value(dev, 1200000);
34 if (ret)
35 return ret;
36 udelay(175); /* Must wait for voltage to stabilize, 2mV/us */
37 ret = regulator_set_value(dev, 1400000);
38 if (ret)
39 return ret;
40 udelay(100); /* Must wait for voltage to stabilize, 2mV/us */
41
42 ret = rockchip_get_clk(&clk.dev);
43 if (ret)
44 return ret;
45 clk.id = PLL_APLL;
46 ret = clk_set_rate(&clk, 1800000000);
47 if (IS_ERR_VALUE(ret))
48 return ret;
49
50 ret = regulator_get_by_platname("vcc33_sd", &dev);
51 if (ret) {
52 debug("Cannot get regulator name\n");
53 return ret;
54 }
55
56 ret = regulator_set_value(dev, 3300000);
57 if (ret)
58 return ret;
59
60 ret = regulators_enable_boot_on(false);
61 if (ret) {
62 debug("%s: Cannot enable boot on regulators\n", __func__);
63 return ret;
64 }
65
66 return 0;
67 }
68 #endif
69
board_early_init_f(void)70 int board_early_init_f(void)
71 {
72 struct udevice *dev;
73 int ret;
74
75 #if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
76 if (!fdt_node_check_compatible(gd->fdt_blob, 0, "google,veyron")) {
77 ret = veyron_init();
78 if (ret)
79 return ret;
80 }
81 #endif
82 /*
83 * This init is done in SPL, but when chain-loading U-Boot SPL will
84 * have been skipped. Allow the clock driver to check if it needs
85 * setting up.
86 */
87 ret = rockchip_get_clk(&dev);
88 if (ret) {
89 debug("CLK init failed: %d\n", ret);
90 return ret;
91 }
92
93 return 0;
94 }
95 #endif
96