1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * K+P iMX6Q KP_IMX6Q_TPC board configuration
4 *
5 * Copyright (C) 2018 Lukasz Majewski <lukma@denx.de>
6 */
7
8 #include <common.h>
9 #include <init.h>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/crm_regs.h>
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/mx6-pins.h>
14 #include <asm/arch/sys_proto.h>
15 #include <asm/mach-imx/boot_mode.h>
16 #include <env.h>
17 #include <errno.h>
18 #include <miiphy.h>
19 #include <usb.h>
20 #include <usb/ehci-ci.h>
21 #include <led.h>
22
23 DECLARE_GLOBAL_DATA_PTR;
24
dram_init(void)25 int dram_init(void)
26 {
27 gd->ram_size = imx_ddr_size();
28 return 0;
29 }
30
31 /*
32 * Do not overwrite the console
33 * Use always serial for U-Boot console
34 */
overwrite_console(void)35 int overwrite_console(void)
36 {
37 return 1;
38 }
39
40 #ifdef CONFIG_FEC_MXC
setup_fec_clock(void)41 static int setup_fec_clock(void)
42 {
43 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
44
45 /* set gpr1[21] to select anatop clock */
46 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK,
47 IOMUXC_GPR1_ENET_CLK_SEL_MASK);
48
49 return enable_fec_anatop_clock(0, ENET_50MHZ);
50 }
51
ar8031_phy_fixup(struct phy_device * phydev)52 static int ar8031_phy_fixup(struct phy_device *phydev)
53 {
54 unsigned short val;
55
56 /* To enable AR8031 output a 125MHz clk from CLK_25M */
57 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
58 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
59 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
60
61 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
62 val &= 0xffe3;
63 val |= 0x18;
64 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
65
66 /* introduce tx clock delay */
67 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
68 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
69 val |= 0x0100;
70 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
71
72 return 0;
73 }
74
board_phy_config(struct phy_device * phydev)75 int board_phy_config(struct phy_device *phydev)
76 {
77 ar8031_phy_fixup(phydev);
78
79 if (phydev->drv->config)
80 phydev->drv->config(phydev);
81
82 return 0;
83 }
84 #endif
85
86 #ifdef CONFIG_USB_EHCI_MX6
setup_usb(void)87 static void setup_usb(void)
88 {
89 /*
90 * Set daisy chain for otg_pin_id on MX6Q.
91 * For MX6DL, this bit is reserved.
92 */
93 imx_iomux_set_gpr_register(1, 13, 1, 0);
94 }
95 #endif
96
board_early_init_f(void)97 int board_early_init_f(void)
98 {
99 #ifdef CONFIG_USB_EHCI_MX6
100 setup_usb();
101 #endif
102
103 #ifdef CONFIG_FEC_MXC
104 setup_fec_clock();
105 #endif
106
107 return 0;
108 }
109
board_init(void)110 int board_init(void)
111 {
112 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
113
114 /* address of boot parameters */
115 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
116
117 /* Enable eim_slow clocks */
118 setbits_le32(&mxc_ccm->CCGR6, 0x1 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET);
119
120 return 0;
121 }
122
123 #ifdef CONFIG_CMD_BMODE
124 static const struct boot_mode board_boot_modes[] = {
125 /* 4 bit bus width */
126 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
127 /* 8 bit bus width */
128 {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
129 {NULL, 0},
130 };
131 #endif
132
board_late_init(void)133 int board_late_init(void)
134 {
135 #ifdef CONFIG_CMD_BMODE
136 add_board_boot_modes(board_boot_modes);
137 #endif
138
139 if (IS_ENABLED(CONFIG_LED))
140 led_default_state();
141
142 env_set("boardname", "kp-tpc");
143 env_set("boardsoc", "imx6q");
144 return 0;
145 }
146
checkboard(void)147 int checkboard(void)
148 {
149 puts("Board: K+P KP_IMX6Q_TPC i.MX6Q\n");
150 return 0;
151 }
152