1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * K+P iMX6Q KP_IMX6Q_TPC board configuration
4 *
5 * Copyright (C) 2018 Lukasz Majewski <lukma@denx.de>
6 */
7
8 #include <common.h>
9 #include <asm/arch/clock.h>
10 #include <asm/arch/crm_regs.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/mx6-ddr.h>
13 #include <asm/arch/sys_proto.h>
14 #include <asm/io.h>
15 #include <errno.h>
16 #include <spl.h>
17
18 DECLARE_GLOBAL_DATA_PTR;
19
ccgr_init(void)20 static void ccgr_init(void)
21 {
22 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
23
24 writel(0x00C03F3F, &ccm->CCGR0);
25 writel(0x0030FC03, &ccm->CCGR1);
26 writel(0x0FFFC000, &ccm->CCGR2);
27 writel(0x3FF00000, &ccm->CCGR3);
28 writel(0x00FFF300, &ccm->CCGR4);
29 writel(0x0F0000C3, &ccm->CCGR5);
30 writel(0x000003FF, &ccm->CCGR6);
31 }
32
33 /* DDR3 */
34 static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
35 .dram_sdclk_0 = 0x00000030,
36 .dram_sdclk_1 = 0x00000030,
37 .dram_cas = 0x00000030,
38 .dram_ras = 0x00000030,
39 .dram_reset = 0x00000030,
40 .dram_sdcke0 = 0x00003000,
41 .dram_sdcke1 = 0x00003000,
42 .dram_sdba2 = 0x00000000,
43 .dram_sdodt0 = 0x00000030,
44 .dram_sdodt1 = 0x00000030,
45
46 .dram_sdqs0 = 0x00000018,
47 .dram_sdqs1 = 0x00000018,
48 .dram_sdqs2 = 0x00000018,
49 .dram_sdqs3 = 0x00000018,
50 .dram_sdqs4 = 0x00000018,
51 .dram_sdqs5 = 0x00000018,
52 .dram_sdqs6 = 0x00000018,
53 .dram_sdqs7 = 0x00000018,
54
55 .dram_dqm0 = 0x00000018,
56 .dram_dqm1 = 0x00000018,
57 .dram_dqm2 = 0x00000018,
58 .dram_dqm3 = 0x00000018,
59 .dram_dqm4 = 0x00000018,
60 .dram_dqm5 = 0x00000018,
61 .dram_dqm6 = 0x00000018,
62 .dram_dqm7 = 0x00000018,
63 };
64
65 static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
66 .grp_ddr_type = 0x000c0000,
67 .grp_ddrmode_ctl = 0x00020000,
68 .grp_ddrpke = 0x00000000,
69 .grp_addds = 0x00000030,
70 .grp_ctlds = 0x00000030,
71 .grp_ddrmode = 0x00020000,
72 .grp_b0ds = 0x00000018,
73 .grp_b1ds = 0x00000018,
74 .grp_b2ds = 0x00000018,
75 .grp_b3ds = 0x00000018,
76 .grp_b4ds = 0x00000018,
77 .grp_b5ds = 0x00000018,
78 .grp_b6ds = 0x00000018,
79 .grp_b7ds = 0x00000018,
80 };
81
82 static const struct mx6_mmdc_calibration mx6_4x256mx16_mmdc_calib = {
83 .p0_mpwldectrl0 = 0x001F001F,
84 .p0_mpwldectrl1 = 0x001F001F,
85 .p1_mpwldectrl0 = 0x001F001F,
86 .p1_mpwldectrl1 = 0x001F001F,
87 .p0_mpdgctrl0 = 0x43270338,
88 .p0_mpdgctrl1 = 0x03200314,
89 .p1_mpdgctrl0 = 0x431A032F,
90 .p1_mpdgctrl1 = 0x03200263,
91 .p0_mprddlctl = 0x4B434748,
92 .p1_mprddlctl = 0x4445404C,
93 .p0_mpwrdlctl = 0x38444542,
94 .p1_mpwrdlctl = 0x4935493A,
95 };
96
97 /* MT41K256M16 (4Gb density) */
98 static const struct mx6_ddr3_cfg mt41k256m16 = {
99 .mem_speed = 1600,
100 .density = 4,
101 .width = 16,
102 .banks = 8,
103 .rowaddr = 15,
104 .coladdr = 10,
105 .pagesz = 2,
106 .trcd = 1375,
107 .trcmin = 4875,
108 .trasmin = 3500,
109 };
110
111 #ifdef CONFIG_MX6_DDRCAL
spl_dram_print_cal(struct mx6_ddr_sysinfo const * sysinfo)112 static void spl_dram_print_cal(struct mx6_ddr_sysinfo const *sysinfo)
113 {
114 struct mx6_mmdc_calibration calibration = {0};
115
116 mmdc_read_calibration(sysinfo, &calibration);
117
118 debug(".p0_mpdgctrl0\t= 0x%08X\n", calibration.p0_mpdgctrl0);
119 debug(".p0_mpdgctrl1\t= 0x%08X\n", calibration.p0_mpdgctrl1);
120 debug(".p0_mprddlctl\t= 0x%08X\n", calibration.p0_mprddlctl);
121 debug(".p0_mpwrdlctl\t= 0x%08X\n", calibration.p0_mpwrdlctl);
122 debug(".p0_mpwldectrl0\t= 0x%08X\n", calibration.p0_mpwldectrl0);
123 debug(".p0_mpwldectrl1\t= 0x%08X\n", calibration.p0_mpwldectrl1);
124 debug(".p1_mpdgctrl0\t= 0x%08X\n", calibration.p1_mpdgctrl0);
125 debug(".p1_mpdgctrl1\t= 0x%08X\n", calibration.p1_mpdgctrl1);
126 debug(".p1_mprddlctl\t= 0x%08X\n", calibration.p1_mprddlctl);
127 debug(".p1_mpwrdlctl\t= 0x%08X\n", calibration.p1_mpwrdlctl);
128 debug(".p1_mpwldectrl0\t= 0x%08X\n", calibration.p1_mpwldectrl0);
129 debug(".p1_mpwldectrl1\t= 0x%08X\n", calibration.p1_mpwldectrl1);
130 }
131
spl_dram_perform_cal(struct mx6_ddr_sysinfo const * sysinfo)132 static void spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo)
133 {
134 int ret;
135
136 /* Perform DDR DRAM calibration */
137 udelay(100);
138 ret = mmdc_do_write_level_calibration(sysinfo);
139 if (ret) {
140 printf("DDR: Write level calibration error [%d]\n", ret);
141 return;
142 }
143
144 ret = mmdc_do_dqs_calibration(sysinfo);
145 if (ret) {
146 printf("DDR: DQS calibration error [%d]\n", ret);
147 return;
148 }
149
150 spl_dram_print_cal(sysinfo);
151 }
152 #endif /* CONFIG_MX6_DDRCAL */
153
spl_dram_init(void)154 static void spl_dram_init(void)
155 {
156 struct mx6_ddr_sysinfo sysinfo = {
157 /* width of data bus:0=16,1=32,2=64 */
158 .dsize = 2,
159 /* config for full 4GB range so that get_mem_size() works */
160 .cs_density = 32, /* 32Gb per CS */
161 /* single chip select */
162 .ncs = 1,
163 .cs1_mirror = 0,
164 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
165 .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */
166 .walat = 1, /* Write additional latency */
167 .ralat = 5, /* Read additional latency */
168 .mif3_mode = 3, /* Command prediction working mode */
169 .bi_on = 1, /* Bank interleaving enabled */
170 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
171 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
172 .pd_fast_exit = 1, /* enable precharge power-down fast exit */
173 .ddr_type = DDR_TYPE_DDR3,
174 .refsel = 1, /* Refresh cycles at 32KHz */
175 .refr = 7, /* 8 refresh commands per refresh cycle */
176 };
177
178 mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
179 mx6_dram_cfg(&sysinfo, &mx6_4x256mx16_mmdc_calib, &mt41k256m16);
180
181 #ifdef CONFIG_MX6_DDRCAL
182 spl_dram_perform_cal(&sysinfo);
183 #endif
184 }
185
board_boot_order(u32 * spl_boot_list)186 void board_boot_order(u32 *spl_boot_list)
187 {
188 u32 boot_device = spl_boot_device();
189 u32 reg = imx6_src_get_boot_mode();
190
191 reg = (reg & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT;
192
193 debug("%s: boot device: 0x%x (0x4 SD, 0x6 eMMC)\n", __func__, reg);
194 if (boot_device == BOOT_DEVICE_MMC1)
195 if (reg == IMX6_BMODE_MMC || reg == IMX6_BMODE_EMMC)
196 boot_device = BOOT_DEVICE_MMC2;
197
198 spl_boot_list[0] = boot_device;
199 /*
200 * Below boot device is a 'fallback' - it shall always be possible to
201 * boot from SD card
202 */
203 spl_boot_list[1] = BOOT_DEVICE_MMC1;
204 }
205
board_init_f(ulong dummy)206 void board_init_f(ulong dummy)
207 {
208 /* setup AIPS and disable watchdog */
209 arch_cpu_init();
210
211 ccgr_init();
212 gpr_init();
213
214 /* setup GP timer */
215 timer_init();
216
217 /* Early - pre reloc - driver model setup */
218 spl_early_init();
219
220 /* UART clocks enabled and gd valid - init serial console */
221 preloader_console_init();
222
223 /* DDR initialization */
224 spl_dram_init();
225
226 /* Clear the BSS. */
227 memset(__bss_start, 0, __bss_end - __bss_start);
228 }
229