1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2006 Freescale Semiconductor, Inc.
4 * Dave Liu <daveliu@freescale.com>
5 *
6 * Copyright (C) 2007 Logic Product Development, Inc.
7 * Peter Barada <peterb@logicpd.com>
8 *
9 * Copyright (C) 2007 MontaVista Software, Inc.
10 * Anton Vorontsov <avorontsov@ru.mvista.com>
11 *
12 * (C) Copyright 2008 - 2010
13 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
14 */
15
16 #include <common.h>
17 #include <env.h>
18 #include <init.h>
19 #include <ioports.h>
20 #include <mpc83xx.h>
21 #include <i2c.h>
22 #include <miiphy.h>
23 #include <asm/io.h>
24 #include <asm/mmu.h>
25 #include <asm/processor.h>
26 #include <pci.h>
27 #include <linux/libfdt.h>
28 #include <post.h>
29
30 #include "../common/common.h"
31
32 DECLARE_GLOBAL_DATA_PTR;
33
34 static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
35
36 const qe_iop_conf_t qe_iop_conf_tab[] = {
37 /* port pin dir open_drain assign */
38 #if defined(CONFIG_ARCH_MPC8360)
39 /* MDIO */
40 {0, 1, 3, 0, 2}, /* MDIO */
41 {0, 2, 1, 0, 1}, /* MDC */
42
43 /* UCC4 - UEC */
44 {1, 14, 1, 0, 1}, /* TxD0 */
45 {1, 15, 1, 0, 1}, /* TxD1 */
46 {1, 20, 2, 0, 1}, /* RxD0 */
47 {1, 21, 2, 0, 1}, /* RxD1 */
48 {1, 18, 1, 0, 1}, /* TX_EN */
49 {1, 26, 2, 0, 1}, /* RX_DV */
50 {1, 27, 2, 0, 1}, /* RX_ER */
51 {1, 24, 2, 0, 1}, /* COL */
52 {1, 25, 2, 0, 1}, /* CRS */
53 {2, 15, 2, 0, 1}, /* TX_CLK - CLK16 */
54 {2, 16, 2, 0, 1}, /* RX_CLK - CLK17 */
55
56 /* DUART - UART2 */
57 {5, 0, 1, 0, 2}, /* UART2_SOUT */
58 {5, 2, 1, 0, 1}, /* UART2_RTS */
59 {5, 3, 2, 0, 2}, /* UART2_SIN */
60 {5, 1, 2, 0, 3}, /* UART2_CTS */
61 #elif !defined(CONFIG_ARCH_MPC8309)
62 /* Local Bus */
63 {0, 16, 1, 0, 3}, /* LA00 */
64 {0, 17, 1, 0, 3}, /* LA01 */
65 {0, 18, 1, 0, 3}, /* LA02 */
66 {0, 19, 1, 0, 3}, /* LA03 */
67 {0, 20, 1, 0, 3}, /* LA04 */
68 {0, 21, 1, 0, 3}, /* LA05 */
69 {0, 22, 1, 0, 3}, /* LA06 */
70 {0, 23, 1, 0, 3}, /* LA07 */
71 {0, 24, 1, 0, 3}, /* LA08 */
72 {0, 25, 1, 0, 3}, /* LA09 */
73 {0, 26, 1, 0, 3}, /* LA10 */
74 {0, 27, 1, 0, 3}, /* LA11 */
75 {0, 28, 1, 0, 3}, /* LA12 */
76 {0, 29, 1, 0, 3}, /* LA13 */
77 {0, 30, 1, 0, 3}, /* LA14 */
78 {0, 31, 1, 0, 3}, /* LA15 */
79
80 /* MDIO */
81 {3, 4, 3, 0, 2}, /* MDIO */
82 {3, 5, 1, 0, 2}, /* MDC */
83
84 /* UCC4 - UEC */
85 {1, 18, 1, 0, 1}, /* TxD0 */
86 {1, 19, 1, 0, 1}, /* TxD1 */
87 {1, 22, 2, 0, 1}, /* RxD0 */
88 {1, 23, 2, 0, 1}, /* RxD1 */
89 {1, 26, 2, 0, 1}, /* RxER */
90 {1, 28, 2, 0, 1}, /* Rx_DV */
91 {1, 30, 1, 0, 1}, /* TxEN */
92 {1, 31, 2, 0, 1}, /* CRS */
93 {3, 10, 2, 0, 3}, /* TxCLK->CLK17 */
94 #endif
95
96 /* END of table */
97 {0, 0, 0, 0, QE_IOP_TAB_END},
98 };
99
100 #if defined(CONFIG_SUVD3)
101 const uint upma_table[] = {
102 0x1ffedc00, 0x0ffcdc80, 0x0ffcdc80, 0x0ffcdc04, /* Words 0 to 3 */
103 0x0ffcdc00, 0xffffcc00, 0xffffcc01, 0xfffffc01, /* Words 4 to 7 */
104 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 8 to 11 */
105 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 12 to 15 */
106 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 16 to 19 */
107 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 20 to 23 */
108 0x9cfffc00, 0x00fffc80, 0x00fffc80, 0x00fffc00, /* Words 24 to 27 */
109 0xffffec04, 0xffffec01, 0xfffffc01, 0xfffffc01, /* Words 28 to 31 */
110 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 32 to 35 */
111 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 36 to 39 */
112 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 40 to 43 */
113 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 44 to 47 */
114 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 48 to 51 */
115 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 52 to 55 */
116 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 56 to 59 */
117 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01 /* Words 60 to 63 */
118 };
119 #endif
120
piggy_present(void)121 static int piggy_present(void)
122 {
123 struct km_bec_fpga __iomem *base =
124 (struct km_bec_fpga __iomem *)CONFIG_SYS_KMBEC_FPGA_BASE;
125
126 return in_8(&base->bprth) & PIGGY_PRESENT;
127 }
128
ethernet_present(void)129 int ethernet_present(void)
130 {
131 return piggy_present();
132 }
133
board_early_init_r(void)134 int board_early_init_r(void)
135 {
136 struct km_bec_fpga *base =
137 (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
138 #if defined(CONFIG_SUVD3)
139 immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
140 fsl_lbc_t *lbc = &immap->im_lbc;
141 u32 *mxmr = &lbc->mamr;
142 #endif
143
144 #if defined(CONFIG_ARCH_MPC8360)
145 unsigned short svid;
146 /*
147 * Because of errata in the UCCs, we have to write to the reserved
148 * registers to slow the clocks down.
149 */
150 svid = SVR_REV(mfspr(SVR));
151 switch (svid) {
152 case 0x0020:
153 /*
154 * MPC8360ECE.pdf QE_ENET10 table 4:
155 * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
156 * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
157 */
158 setbits_be32((void *)(CONFIG_SYS_IMMR + 0x14a8), 0x0c003000);
159 break;
160 case 0x0021:
161 /*
162 * MPC8360ECE.pdf QE_ENET10 table 4:
163 * IMMR + 0x14AC[24:27] = 1010
164 */
165 clrsetbits_be32((void *)(CONFIG_SYS_IMMR + 0x14ac),
166 0x00000050, 0x000000a0);
167 break;
168 }
169 #endif
170
171 /* enable the PHY on the PIGGY */
172 setbits_8(&base->pgy_eth, 0x01);
173 /* enable the Unit LED (green) */
174 setbits_8(&base->oprth, WRL_BOOT);
175 /* enable Application Buffer */
176 setbits_8(&base->oprtl, OPRTL_XBUFENA);
177
178 #if defined(CONFIG_SUVD3)
179 /* configure UPMA for APP1 */
180 upmconfig(UPMA, (uint *) upma_table,
181 sizeof(upma_table) / sizeof(uint));
182 out_be32(mxmr, CONFIG_SYS_MAMR);
183 #endif
184 return 0;
185 }
186
misc_init_r(void)187 int misc_init_r(void)
188 {
189 ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
190 return 0;
191 }
192
last_stage_init(void)193 int last_stage_init(void)
194 {
195 #if defined(CONFIG_TARGET_KMCOGE5NE)
196 struct bfticu_iomap *base =
197 (struct bfticu_iomap *)CONFIG_SYS_BFTIC3_BASE;
198 u8 dip_switch = in_8((u8 *)&(base->mswitch)) & BFTICU_DIPSWITCH_MASK;
199
200 if (dip_switch != 0) {
201 /* start bootloader */
202 puts("DIP: Enabled\n");
203 env_set("actual_bank", "0");
204 }
205 #endif
206 set_km_env();
207 return 0;
208 }
209
fixed_sdram(void)210 static int fixed_sdram(void)
211 {
212 immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
213 u32 msize = 0;
214 u32 ddr_size;
215 u32 ddr_size_log2;
216
217 out_be32(&im->sysconf.ddrlaw[0].ar, (LAWAR_EN | 0x1e));
218 out_be32(&im->ddr.csbnds[0].csbnds, (CONFIG_SYS_DDR_CS0_BNDS) | 0x7f);
219 out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
220 out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
221 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
222 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
223 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
224 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
225 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
226 out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
227 out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
228 out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
229 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
230 udelay(200);
231 setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
232
233 msize = CONFIG_SYS_DDR_SIZE << 20;
234 disable_addr_trans();
235 msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
236 enable_addr_trans();
237 msize /= (1024 * 1024);
238 if (CONFIG_SYS_DDR_SIZE != msize) {
239 for (ddr_size = msize << 20, ddr_size_log2 = 0;
240 (ddr_size > 1);
241 ddr_size = ddr_size >> 1, ddr_size_log2++)
242 if (ddr_size & 1)
243 return -1;
244 out_be32(&im->sysconf.ddrlaw[0].ar,
245 (LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE)));
246 out_be32(&im->ddr.csbnds[0].csbnds,
247 (((msize / 16) - 1) & 0xff));
248 }
249
250 return msize;
251 }
252
dram_init(void)253 int dram_init(void)
254 {
255 immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
256 u32 msize = 0;
257
258 if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
259 return -ENXIO;
260
261 out_be32(&im->sysconf.ddrlaw[0].bar,
262 CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR);
263 msize = fixed_sdram();
264
265 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
266 /*
267 * Initialize DDR ECC byte
268 */
269 ddr_enable_ecc(msize * 1024 * 1024);
270 #endif
271
272 /* return total bus SDRAM size(bytes) -- DDR */
273 gd->ram_size = msize * 1024 * 1024;
274
275 return 0;
276 }
277
checkboard(void)278 int checkboard(void)
279 {
280 puts("Board: Keymile " CONFIG_KM_BOARD_NAME);
281
282 if (piggy_present())
283 puts(" with PIGGY.");
284 puts("\n");
285 return 0;
286 }
287
ft_board_setup(void * blob,bd_t * bd)288 int ft_board_setup(void *blob, bd_t *bd)
289 {
290 ft_cpu_setup(blob, bd);
291
292 return 0;
293 }
294
295 #if defined(CONFIG_HUSH_INIT_VAR)
hush_init_var(void)296 int hush_init_var(void)
297 {
298 ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
299 return 0;
300 }
301 #endif
302
303 #if defined(CONFIG_POST)
post_hotkeys_pressed(void)304 int post_hotkeys_pressed(void)
305 {
306 int testpin = 0;
307 struct km_bec_fpga *base =
308 (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
309 int testpin_reg = in_8(&base->CONFIG_TESTPIN_REG);
310 testpin = (testpin_reg & CONFIG_TESTPIN_MASK) != 0;
311 debug("post_hotkeys_pressed: %d\n", !testpin);
312 return testpin;
313 }
314
post_word_load(void)315 ulong post_word_load(void)
316 {
317 void* addr = (ulong *) (CPM_POST_WORD_ADDR);
318 debug("post_word_load 0x%08lX: 0x%08X\n", (ulong)addr, in_le32(addr));
319 return in_le32(addr);
320
321 }
post_word_store(ulong value)322 void post_word_store(ulong value)
323 {
324 void* addr = (ulong *) (CPM_POST_WORD_ADDR);
325 debug("post_word_store 0x%08lX: 0x%08lX\n", (ulong)addr, value);
326 out_le32(addr, value);
327 }
328
arch_memory_test_prepare(u32 * vstart,u32 * size,phys_addr_t * phys_offset)329 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
330 {
331 *vstart = CONFIG_SYS_MEMTEST_START;
332 *size = CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START;
333 debug("arch_memory_test_prepare 0x%08X 0x%08X\n", *vstart, *size);
334
335 return 0;
336 }
337 #endif
338