1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2013 Keymile AG
4 * Valentin Longchamp <valentin.longchamp@keymile.com>
5 *
6 * Copyright 2011,2012 Freescale Semiconductor, Inc.
7 */
8
9 #include <common.h>
10 #include <command.h>
11 #include <env.h>
12 #include <init.h>
13 #include <netdev.h>
14 #include <linux/compiler.h>
15 #include <asm/mmu.h>
16 #include <asm/processor.h>
17 #include <asm/cache.h>
18 #include <asm/immap_85xx.h>
19 #include <asm/fsl_law.h>
20 #include <asm/fsl_serdes.h>
21 #include <asm/fsl_portals.h>
22 #include <asm/fsl_liodn.h>
23 #include <fm_eth.h>
24
25 #include "../common/common.h"
26 #include "kmp204x.h"
27
28 static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
29
checkboard(void)30 int checkboard(void)
31 {
32 printf("Board: Keymile %s\n", CONFIG_KM_BOARD_NAME);
33
34 return 0;
35 }
36
37 /* I2C deblocking uses the algorithm defined in board/keymile/common/common.c
38 * 2 dedicated QRIO GPIOs externally pull the SCL and SDA lines
39 * For I2C only the low state is activly driven and high state is pulled-up
40 * by a resistor. Therefore the deblock GPIOs are used
41 * -> as an active output to drive a low state
42 * -> as an open-drain input to have a pulled-up high state
43 */
44
45 /* QRIO GPIOs used for deblocking */
46 #define DEBLOCK_PORT1 GPIO_A
47 #define DEBLOCK_SCL1 20
48 #define DEBLOCK_SDA1 21
49
50 /* By default deblock GPIOs are floating */
i2c_deblock_gpio_cfg(void)51 static void i2c_deblock_gpio_cfg(void)
52 {
53 /* set I2C bus 1 deblocking GPIOs input, but 0 value for open drain */
54 qrio_gpio_direction_input(DEBLOCK_PORT1, DEBLOCK_SCL1);
55 qrio_gpio_direction_input(DEBLOCK_PORT1, DEBLOCK_SDA1);
56
57 qrio_set_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1, 0);
58 qrio_set_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1, 0);
59 }
60
set_sda(int state)61 void set_sda(int state)
62 {
63 qrio_set_opendrain_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1, state);
64 }
65
set_scl(int state)66 void set_scl(int state)
67 {
68 qrio_set_opendrain_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1, state);
69 }
70
get_sda(void)71 int get_sda(void)
72 {
73 return qrio_get_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1);
74 }
75
get_scl(void)76 int get_scl(void)
77 {
78 return qrio_get_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1);
79 }
80
81
82 #define ZL30158_RST 8
83 #define BFTIC4_RST 0
84 #define RSTRQSR1_WDT_RR 0x00200000
85 #define RSTRQSR1_SW_RR 0x00100000
86
board_early_init_f(void)87 int board_early_init_f(void)
88 {
89 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
90 bool cpuwd_flag = false;
91
92 /* configure mode for uP reset request */
93 qrio_uprstreq(UPREQ_CORE_RST);
94
95 /* board only uses the DDR_MCK0, so disable the DDR_MCK1/2/3 */
96 setbits_be32(&gur->ddrclkdr, 0x001f000f);
97
98 /* set reset reason according CPU register */
99 if ((gur->rstrqsr1 & (RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR)) ==
100 RSTRQSR1_WDT_RR)
101 cpuwd_flag = true;
102
103 qrio_cpuwd_flag(cpuwd_flag);
104 /* clear CPU bits by writing 1 */
105 setbits_be32(&gur->rstrqsr1, RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR);
106
107 /* set the BFTIC's prstcfg to reset at power-up and unit reset only */
108 qrio_prstcfg(BFTIC4_RST, PRSTCFG_POWUP_UNIT_RST);
109 /* and enable WD on it */
110 qrio_wdmask(BFTIC4_RST, true);
111
112 /* set the ZL30138's prstcfg to reset at power-up only */
113 qrio_prstcfg(ZL30158_RST, PRSTCFG_POWUP_RST);
114 /* and take it out of reset as soon as possible (needed for Hooper) */
115 qrio_prst(ZL30158_RST, false, false);
116
117 return 0;
118 }
119
board_early_init_r(void)120 int board_early_init_r(void)
121 {
122 int ret = 0;
123 /* Flush d-cache and invalidate i-cache of any FLASH data */
124 flush_dcache();
125 invalidate_icache();
126
127 set_liodns();
128 setup_qbman_portals();
129
130 ret = trigger_fpga_config();
131 if (ret)
132 printf("error triggering PCIe FPGA config\n");
133
134 /* enable the Unit LED (red) & Boot LED (on) */
135 qrio_set_leds();
136
137 /* enable Application Buffer */
138 qrio_enable_app_buffer();
139
140 return ret;
141 }
142
get_board_sys_clk(unsigned long dummy)143 unsigned long get_board_sys_clk(unsigned long dummy)
144 {
145 return 66666666;
146 }
147
148 #define ETH_FRONT_PHY_RST 15
149 #define QSFP2_RST 11
150 #define QSFP1_RST 10
151 #define ZL30343_RST 9
152
misc_init_f(void)153 int misc_init_f(void)
154 {
155 /* configure QRIO pis for i2c deblocking */
156 i2c_deblock_gpio_cfg();
157
158 /* configure the front phy's prstcfg and take it out of reset */
159 qrio_prstcfg(ETH_FRONT_PHY_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
160 qrio_prst(ETH_FRONT_PHY_RST, false, false);
161
162 /* set the ZL30343 prstcfg to reset at power-up only */
163 qrio_prstcfg(ZL30343_RST, PRSTCFG_POWUP_RST);
164 /* and enable the WD on it */
165 qrio_wdmask(ZL30343_RST, true);
166
167 /* set the QSFPs' prstcfg to reset at power-up and unit rst only */
168 qrio_prstcfg(QSFP1_RST, PRSTCFG_POWUP_UNIT_RST);
169 qrio_prstcfg(QSFP2_RST, PRSTCFG_POWUP_UNIT_RST);
170
171 /* and enable the WD on them */
172 qrio_wdmask(QSFP1_RST, true);
173 qrio_wdmask(QSFP2_RST, true);
174
175 return 0;
176 }
177
178 #define NUM_SRDS_BANKS 2
179
misc_init_r(void)180 int misc_init_r(void)
181 {
182 serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
183 u32 expected[NUM_SRDS_BANKS] = {SRDS_PLLCR0_RFCK_SEL_100,
184 SRDS_PLLCR0_RFCK_SEL_125};
185 unsigned int i;
186
187 /* check SERDES reference clocks */
188 for (i = 0; i < NUM_SRDS_BANKS; i++) {
189 u32 actual = in_be32(®s->bank[i].pllcr0);
190 actual &= SRDS_PLLCR0_RFCK_SEL_MASK;
191 if (actual != expected[i]) {
192 printf("Warning: SERDES bank %u expects reference \
193 clock %sMHz, but actual is %sMHz\n", i + 1,
194 serdes_clock_to_string(expected[i]),
195 serdes_clock_to_string(actual));
196 }
197 }
198
199 ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
200 return 0;
201 }
202
203 #if defined(CONFIG_HUSH_INIT_VAR)
hush_init_var(void)204 int hush_init_var(void)
205 {
206 ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
207 return 0;
208 }
209 #endif
210
211 #if defined(CONFIG_LAST_STAGE_INIT)
212
last_stage_init(void)213 int last_stage_init(void)
214 {
215 #if defined(CONFIG_KMCOGE4)
216 /* on KMCOGE4, the BFTIC4 is on the LBAPP2 */
217 struct bfticu_iomap *bftic4 =
218 (struct bfticu_iomap *)CONFIG_SYS_LBAPP2_BASE;
219 u8 dip_switch = in_8((u8 *)&(bftic4->mswitch)) & BFTICU_DIPSWITCH_MASK;
220
221 if (dip_switch != 0) {
222 /* start bootloader */
223 puts("DIP: Enabled\n");
224 env_set("actual_bank", "0");
225 }
226 #endif
227 set_km_env();
228
229 return 0;
230 }
231 #endif
232
233 #ifdef CONFIG_SYS_DPAA_FMAN
fdt_fixup_fman_mac_addresses(void * blob)234 void fdt_fixup_fman_mac_addresses(void *blob)
235 {
236 int node, i, ret;
237 char *tmp, *end;
238 unsigned char mac_addr[6];
239
240 /* get the mac addr from env */
241 tmp = env_get("ethaddr");
242 if (!tmp) {
243 printf("ethaddr env variable not defined\n");
244 return;
245 }
246 for (i = 0; i < 6; i++) {
247 mac_addr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
248 if (tmp)
249 tmp = (*end) ? end+1 : end;
250 }
251
252 /* find the correct fdt ethernet path and correct it */
253 node = fdt_path_offset(blob, "/soc/fman/ethernet@e8000");
254 if (node < 0) {
255 printf("no /soc/fman/ethernet path offset\n");
256 return;
257 }
258 ret = fdt_setprop(blob, node, "local-mac-address", &mac_addr, 6);
259 if (ret) {
260 printf("error setting local-mac-address property\n");
261 return;
262 }
263 }
264 #endif
265
ft_board_setup(void * blob,bd_t * bd)266 int ft_board_setup(void *blob, bd_t *bd)
267 {
268 phys_addr_t base;
269 phys_size_t size;
270
271 ft_cpu_setup(blob, bd);
272
273 base = env_get_bootm_low();
274 size = env_get_bootm_size();
275
276 fdt_fixup_memory(blob, (u64)base, (u64)size);
277
278 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
279 fsl_fdt_fixup_dr_usb(blob, bd);
280 #endif
281
282 #ifdef CONFIG_PCI
283 pci_of_setup(blob, bd);
284 #endif
285
286 fdt_fixup_liodn(blob);
287 #ifdef CONFIG_SYS_DPAA_FMAN
288 fdt_fixup_fman_ethernet(blob);
289 fdt_fixup_fman_mac_addresses(blob);
290 #endif
291
292 return 0;
293 }
294
295 #if defined(CONFIG_POST)
296
297 /* DIC26_SELFTEST GPIO used to start factory test sw */
298 #define SELFTEST_PORT GPIO_A
299 #define SELFTEST_PIN 31
300
post_hotkeys_pressed(void)301 int post_hotkeys_pressed(void)
302 {
303 qrio_gpio_direction_input(SELFTEST_PORT, SELFTEST_PIN);
304 return qrio_get_gpio(SELFTEST_PORT, SELFTEST_PIN);
305 }
306 #endif
307