1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2017 Logic PD, Inc.
4 *
5 * Author: Adam Ford <aford173@gmail.com>
6 *
7 * Based on SabreSD by Fabio Estevam <fabio.estevam@nxp.com>
8 * and updates by Jagan Teki <jagan@amarulasolutions.com>
9 */
10
11 #include <common.h>
12 #include <env.h>
13 #include <init.h>
14 #include <miiphy.h>
15 #include <input.h>
16 #include <mmc.h>
17 #include <fsl_esdhc_imx.h>
18 #include <serial.h>
19 #include <asm/io.h>
20 #include <asm/gpio.h>
21 #include <linux/sizes.h>
22 #include <asm/arch/clock.h>
23 #include <asm/arch/crm_regs.h>
24 #include <asm/arch/iomux.h>
25 #include <asm/arch/mxc_hdmi.h>
26 #include <asm/arch/mx6-pins.h>
27 #include <asm/arch/sys_proto.h>
28 #include <asm/mach-imx/boot_mode.h>
29 #include <asm/mach-imx/iomux-v3.h>
30
31 DECLARE_GLOBAL_DATA_PTR;
32
33 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
34 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
35 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
36
37 #define NAND_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
38 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
39 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
40
dram_init(void)41 int dram_init(void)
42 {
43 gd->ram_size = imx_ddr_size();
44 return 0;
45 }
46
47 static iomux_v3_cfg_t const nand_pads[] = {
48 MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
49 MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
50 MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
51 MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
52 MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
53 MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
54 MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
55 MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
56 MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
57 MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
58 MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
59 MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
60 MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
61 MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
62 MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
63 };
64
setup_nand_pins(void)65 static void setup_nand_pins(void)
66 {
67 imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
68 }
69
ar8031_phy_fixup(struct phy_device * phydev)70 static int ar8031_phy_fixup(struct phy_device *phydev)
71 {
72 unsigned short val;
73
74 /* To enable AR8031 output a 125MHz clk from CLK_25M */
75 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
76 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
77 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
78
79 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
80 val &= 0xffe3;
81 val |= 0x18;
82 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
83
84 /* introduce tx clock delay */
85 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
86 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
87 val |= 0x0100;
88 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
89
90 return 0;
91 }
92
board_phy_config(struct phy_device * phydev)93 int board_phy_config(struct phy_device *phydev)
94 {
95 ar8031_phy_fixup(phydev);
96
97 if (phydev->drv->config)
98 phydev->drv->config(phydev);
99
100 return 0;
101 }
102
103 /*
104 * Do not overwrite the console
105 * Use always serial for U-Boot console
106 */
overwrite_console(void)107 int overwrite_console(void)
108 {
109 return 1;
110 }
111
board_early_init_f(void)112 int board_early_init_f(void)
113 {
114 setup_nand_pins();
115 return 0;
116 }
117
board_init(void)118 int board_init(void)
119 {
120 /* address of boot parameters */
121 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
122 return 0;
123 }
124
board_late_init(void)125 int board_late_init(void)
126 {
127 env_set("board_name", "imx6logic");
128
129 if (is_mx6dq()) {
130 env_set("board_rev", "MX6DQ");
131 if (!env_get("fdt_file"))
132 env_set("fdt_file", "imx6q-logicpd.dtb");
133 }
134
135 return 0;
136 }
137
138 #ifdef CONFIG_SPL_BUILD
139 #include <asm/arch/mx6-ddr.h>
140 #include <asm/arch/mx6q-ddr.h>
141 #include <spl.h>
142 #include <linux/libfdt.h>
143
144 #ifdef CONFIG_SPL_OS_BOOT
spl_start_uboot(void)145 int spl_start_uboot(void)
146 {
147 /* break into full u-boot on 'c' */
148 if (serial_tstc() && serial_getc() == 'c')
149 return 1;
150
151 return 0;
152 }
153 #endif
154
board_boot_order(u32 * spl_boot_list)155 void board_boot_order(u32 *spl_boot_list)
156 {
157 struct src *psrc = (struct src *)SRC_BASE_ADDR;
158 unsigned int reg = readl(&psrc->sbmr1) >> 11;
159 u32 boot_mode = imx6_src_get_boot_mode() & IMX6_BMODE_MASK;
160 unsigned int bmode = readl(&src_base->sbmr2);
161
162 /* If bmode is serial or USB phy is active, return serial */
163 if (((bmode >> 24) & 0x03) == 0x01 || is_usbotg_phy_active()) {
164 spl_boot_list[0] = BOOT_DEVICE_BOARD;
165 return;
166 }
167
168 switch (boot_mode >> IMX6_BMODE_SHIFT) {
169 case IMX6_BMODE_NAND_MIN ... IMX6_BMODE_NAND_MAX:
170 spl_boot_list[0] = BOOT_DEVICE_NAND;
171 break;
172 case IMX6_BMODE_SD:
173 case IMX6_BMODE_ESD:
174 case IMX6_BMODE_MMC:
175 case IMX6_BMODE_EMMC:
176 /*
177 * Upon reading BOOT_CFG register the following map is done:
178 * Bit 11 and 12 of BOOT_CFG register can determine the current
179 * mmc port
180 * 0x1 SD1-SOM
181 * 0x2 SD2-Baseboard
182 */
183
184 reg &= 0x3; /* Only care about bottom 2 bits */
185 switch (reg) {
186 case 0:
187 spl_boot_list[0] = BOOT_DEVICE_MMC1;
188 break;
189 case 1:
190 spl_boot_list[0] = BOOT_DEVICE_MMC2;
191 break;
192 }
193 break;
194 default:
195 /* By default use USB downloader */
196 spl_boot_list[0] = BOOT_DEVICE_BOARD;
197 break;
198 }
199
200 /* As a last resort, use serial downloader */
201 spl_boot_list[1] = BOOT_DEVICE_BOARD;
202 }
203
ccgr_init(void)204 static void ccgr_init(void)
205 {
206 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
207
208 writel(0x00C03F3F, &ccm->CCGR0);
209 writel(0x0030FC03, &ccm->CCGR1);
210 writel(0x0FFFC000, &ccm->CCGR2);
211 writel(0x3FF00000, &ccm->CCGR3);
212 writel(0xFFFFF300, &ccm->CCGR4);
213 writel(0x0F0000F3, &ccm->CCGR5);
214 writel(0x00000FFF, &ccm->CCGR6);
215 }
216
217 static int mx6q_dcd_table[] = {
218 MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
219 MX6_IOM_GRP_DDRPKE, 0x00000000,
220 MX6_IOM_DRAM_SDCLK_0, 0x00000030,
221 MX6_IOM_DRAM_SDCLK_1, 0x00000030,
222 MX6_IOM_DRAM_CAS, 0x00000030,
223 MX6_IOM_DRAM_RAS, 0x00000030,
224 MX6_IOM_GRP_ADDDS, 0x00000030,
225 MX6_IOM_DRAM_RESET, 0x00000030,
226 MX6_IOM_DRAM_SDBA2, 0x00000000,
227 MX6_IOM_DRAM_SDODT0, 0x00000030,
228 MX6_IOM_DRAM_SDODT1, 0x00000030,
229 MX6_IOM_GRP_CTLDS, 0x00000030,
230 MX6_IOM_DDRMODE_CTL, 0x00020000,
231 MX6_IOM_DRAM_SDQS0, 0x00000030,
232 MX6_IOM_DRAM_SDQS1, 0x00000030,
233 MX6_IOM_DRAM_SDQS2, 0x00000030,
234 MX6_IOM_DRAM_SDQS3, 0x00000030,
235 MX6_IOM_GRP_DDRMODE, 0x00020000,
236 MX6_IOM_GRP_B0DS, 0x00000030,
237 MX6_IOM_GRP_B1DS, 0x00000030,
238 MX6_IOM_GRP_B2DS, 0x00000030,
239 MX6_IOM_GRP_B3DS, 0x00000030,
240 MX6_IOM_DRAM_DQM0, 0x00000030,
241 MX6_IOM_DRAM_DQM1, 0x00000030,
242 MX6_IOM_DRAM_DQM2, 0x00000030,
243 MX6_IOM_DRAM_DQM3, 0x00000030,
244 MX6_MMDC_P0_MDSCR, 0x00008000,
245 MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
246 MX6_MMDC_P0_MPWLDECTRL0, 0x002D003A,
247 MX6_MMDC_P0_MPWLDECTRL1, 0x0038002B,
248 MX6_MMDC_P0_MPDGCTRL0, 0x03340338,
249 MX6_MMDC_P0_MPDGCTRL1, 0x0334032C,
250 MX6_MMDC_P0_MPRDDLCTL, 0x4036383C,
251 MX6_MMDC_P0_MPWRDLCTL, 0x2E384038,
252 MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
253 MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
254 MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
255 MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
256 MX6_MMDC_P0_MPMUR0, 0x00000800,
257 MX6_MMDC_P0_MDPDC, 0x00020036,
258 MX6_MMDC_P0_MDOTC, 0x09444040,
259 MX6_MMDC_P0_MDCFG0, 0xB8BE7955,
260 MX6_MMDC_P0_MDCFG1, 0xFF328F64,
261 MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
262 MX6_MMDC_P0_MDMISC, 0x00011740,
263 MX6_MMDC_P0_MDSCR, 0x00008000,
264 MX6_MMDC_P0_MDRWD, 0x000026D2,
265 MX6_MMDC_P0_MDOR, 0x00BE1023,
266 MX6_MMDC_P0_MDASP, 0x00000047,
267 MX6_MMDC_P0_MDCTL, 0x85190000,
268 MX6_MMDC_P0_MDSCR, 0x00888032,
269 MX6_MMDC_P0_MDSCR, 0x00008033,
270 MX6_MMDC_P0_MDSCR, 0x00008031,
271 MX6_MMDC_P0_MDSCR, 0x19408030,
272 MX6_MMDC_P0_MDSCR, 0x04008040,
273 MX6_MMDC_P0_MDREF, 0x00007800,
274 MX6_MMDC_P0_MPODTCTRL, 0x00000007,
275 MX6_MMDC_P0_MDPDC, 0x00025576,
276 MX6_MMDC_P0_MAPSR, 0x00011006,
277 MX6_MMDC_P0_MDSCR, 0x00000000,
278 /* enable AXI cache for VDOA/VPU/IPU */
279
280 MX6_IOMUXC_GPR4, 0xF00000CF,
281 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
282 MX6_IOMUXC_GPR6, 0x007F007F,
283 MX6_IOMUXC_GPR7, 0x007F007F,
284 };
285
ddr_init(int * table,int size)286 static void ddr_init(int *table, int size)
287 {
288 int i;
289
290 for (i = 0; i < size / 2 ; i++)
291 writel(table[2 * i + 1], table[2 * i]);
292 }
293
spl_dram_init(void)294 static void spl_dram_init(void)
295 {
296 if (is_mx6dq())
297 ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
298 }
299
board_init_f(ulong dummy)300 void board_init_f(ulong dummy)
301 {
302 /* DDR initialization */
303 spl_dram_init();
304
305 /* setup AIPS and disable watchdog */
306 arch_cpu_init();
307
308 ccgr_init();
309 gpr_init();
310
311 /* iomux and setup of uart and NAND pins */
312 board_early_init_f();
313
314 /* setup GP timer */
315 timer_init();
316
317 /* Enable device tree and early DM support*/
318 spl_early_init();
319
320 /* UART clocks enabled and gd valid - init serial console */
321 preloader_console_init();
322 }
323 #endif
324