1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2017 Renesas Electronics 4 * Copyright (C) Chris Brandt 5 */ 6 7 #include <common.h> 8 #include <asm/io.h> 9 #include <asm/arch/sys_proto.h> 10 11 #define RZA1_WDT_BASE 0xfcfe0000 12 #define WTCSR 0x00 13 #define WTCNT 0x02 14 #define WRCSR 0x04 15 16 DECLARE_GLOBAL_DATA_PTR; 17 board_init(void)18int board_init(void) 19 { 20 gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100); 21 22 return 0; 23 } 24 dram_init(void)25int dram_init(void) 26 { 27 if (fdtdec_setup_mem_size_base() != 0) 28 return -EINVAL; 29 30 return 0; 31 } 32 dram_init_banksize(void)33int dram_init_banksize(void) 34 { 35 fdtdec_setup_memory_banksize(); 36 37 return 0; 38 } 39 reset_cpu(ulong addr)40void reset_cpu(ulong addr) 41 { 42 /* Dummy read (must read WRCSR:WOVF at least once before clearing) */ 43 readb(RZA1_WDT_BASE + WRCSR); 44 45 writew(0xa500, RZA1_WDT_BASE + WRCSR); 46 writew(0x5a5f, RZA1_WDT_BASE + WRCSR); 47 writew(0x5a00, RZA1_WDT_BASE + WTCNT); 48 writew(0xa578, RZA1_WDT_BASE + WTCSR); 49 50 for (;;) 51 asm volatile("wfi"); 52 } 53